`timescale 1 ns / 1 ps
module counter(clk_48m,reset_n,led);
input clk_48m; // 系统时钟
input reset_n; // 系统复位信号,低电平复位
output [7:0] led; // 计数值输出 // 分频系数,分到2s周期,便于观察
parameter cnt_top = 26'd48000000; // 分频系数,分到2s周期,便于观察
reg clk_2s; // 分频后的时钟输出
reg [25:0] clk_cnt;
reg [7:0] led;
reg [1:0] nstep;
always @(posedge clk_48m or negedge reset_n)
begin
if(!reset_n)
begin
clk_2s <= 1'b0;
clk_cnt <= 26'd0;
end
else if(clk_cnt == cnt_top-1'b1)
begin
clk_cnt <= 26'd0;
clk_2s <= ~clk_2s;
end
else
begin
clk_cnt <= clk_cnt + 1'b1;
clk_2s <= clk_2s;
end
end
always @(posedge clk_2s or negedge reset_n)
begin
if(!reset_n)
led <= 8'b11110000;
if(nstep==2'b00) led <=8'b00010000;
else if(nstep==2'b01) led <=8'b00100000;
else if(nstep==2'b10) led <=8'b01000000;
else if(nstep==2'b11) led <=8'b10000000;
nstep<=nstep+1'b1;
end
endmodule
主要实现2S流水灯,谢谢! |