Introduction
Electrical overstress (EOS) has historically been one of the leading causes of integrated circuit failures, regardless
of the semiconductor manufacturer. In general terms, electrical overstress can be defined as any condition where
one or more pins on an IC are subjected to current and/or voltage levels that exceed the Absolute Maximum Ratings
per the IC data sheet. The result of an EOS event can range from no damage or degradation to the IC up to
catastrophic damage where the IC is permanently non-functional. EOS covers a broad spectrum of events,
including electrostatic discharge (ESD), latch-up, power-up/power-down transients, and excessive DC
current/voltage levels. ESD is typically the most common form of EOS, and consequently it is the focus of much
of this chapter.
ADI recognizes the need to design ICs that are robust to all forms of EOS in order to maximize manufacturability
and minimize customer failures. Over the past three decades, ADI has developed extensive expertise in designing
ICs that are robust to EOS. In the 1970s, ICs were designed on relatively large geometry fabrication processes that
inherently provided good robustness. Since the 1980s, as process geometries have shrunken, ADI has developed
design rules and proprietary design techniques for providing adequate on-chip EOS protection. ADI holds many
patents for novel on-chip EOS protection circuits for products on bipolar, bipolar-CMOS, and CMOS processes.
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