RK3576、RK3576J、RK3576M套片&开发板&核心板

只看该作者 · 2025-1-13 11:03

#每日话题#1 OverviewRK3576 is a low power, high performance processor for ARM-based PC and Edge Computing
device, personal mobile internet device and other digital multimedia applications, and
integrates quad-core Cortex-A72 and quad-core Cortex-A53 with separately NEON
coprocessor.
RK3576 video decoder supports H.264, H.265, VP9, AV1 and AVS2 etc. up to 8K@30fps or
4K@120fps, and video encoder supports H.264 and H.265 up to 4K@60fps, high-quality
JPEG encoder/decoder supports up to 4K@60fps.
Embedded 3D GPU makes RK3576 completely compatible with OpenGL ES 1.1, 2.0, and
3.2, OpenCL up to 2.0 and Vulkan 1.1. Dedicated 2D hardware engine with MMU will
maximize display performance and provide very smoothly operation.
RK3576 introduces a new generation 16-Megapixel ISP (Image Signal Processor). It
implements a lot of algorithm accelerators, such as HDR, 3A, CAC, 3DNR, 2DNR,
Sharpening, Dehaze, Enhance, Debayer, Small Angle Lens-Distortion Correction and so on.
The build-in NPU supports INT4/INT8/INT16/FP16/BF16/TF32 hybrid operation. In addition,
with its strong compatibility, network models based on a series of frameworks such as
TensorFlow/MXNet/PyTorch/Caffe can be easily converted.
RK3576 supports high-performance dual channel external memory interface
(LPDDR4/LPDDR4X/LPDDR5) capable of sustaining demanding memory bandwidths, also
provides a complete set of peripheral interface to support very flexible applications.
1.2 Features
1.2.1 Microprocessor
 Cortex A72 cluster
 Quad Cortex A72 MPCore processor
 48kB L1 instruction cache and 32kB L1 data cache for each core
 1MB unified L2 cache
 Cortex A53 cluster
 Quad Cortex A53 MPCore processor
 32kB L1 instruction cache and 32kB L1 data cache for each core
 512kB unified L2 cache
Copyright ©2024 Rockchip Electronics Co., Ltd. 7RK3576 Datasheet Rev 1.1
 TrustZone technology
 ARMv8 Cryptography Extensions
 Full implementation of the ARM architecture v8-A instruction set, ARM Neon Advanced
SIMD (single instruction, multiple data) support for accelerating media and signal
processing
 Two isolated voltage domains to support DVFS, one is for A72 cluster and the other is
for A53 cluster.
 Independent power domain for each CPU core system (CPU+Neon+FPU+L1 cache).
1.2.2 Memory Organization
 Internal on-chip memory
 BootRom
 Supports system boot from the following devices:
 FSPI interface
 eMMC interface
 UFS interface
 SD card interface
 USB interface
 Supports system code download by the following interface:
 USB OTG interface
 PMU_SRAM (32kB) is for low power application
 SYS_SRAM (512kB) may be shared by any on-chip components
 External off-chip memory
 Dynamic Memory interface
 JEDEC standards LPDDR4/LPDDR4X-4266 and LPDDR5-4800.
 Dual channels, each channel has 16bits data width.
 Up to 2 ranks (chip select) for each channel.
 Up to 16GB addressing space totally.
 Low power mode including power-down and self-refresh with power-down.
 eMMC interface
 Compliance to JEDEC eMMC v5.1 specification
 Compatible to eMMC 4.51 and earlier versions specification.
 Supports HS400, HS200, DDR50 and legacy operating modes
 Supports data bus width: 1-bit, 4-bit or 8-bit
 SD/MMC interface
 Compliance to SD v3.0, MMC v4.51
 Supports 4-bit data bus
 UFS interface
 Compatible to UFS v2.0 specification
Copyright ©2024 Rockchip Electronics Co., Ltd. 8RK3576 Datasheet Rev 1.1
 Supports 2 data lanes
 Up to High-Speed Gear 3 (HS-G3)
 Flexible Serial Flash Interface(FSPI)
 Supports serial NOR, NAND, pSRAM, SRAM devices
 Supports 1-bit, 2-bit, and 4-bit data width
 Supports 2 chip selects for 1-bit, 2-bit, 4-bit FSPI
1.2.3 System Component
 MCU
 Single core Cortex M0
 16kB unified I/D cache
 Programmable Interrupt Controller
 JTAG interface for debug
 CRU (clock & reset unit)
 Supports 12 PLLs to generate all clocks totally
 Supports one 24MHz oscillator as input
 Supports clock gating control for individual components
 Supports global soft-reset control for whole chip, also individual soft-reset for each
component
 PMU (power management unit)
 Supports multiple configurable work modes to save power consumption with
different frequency or automatic clock gating control or power domain control
 Supports many wakeup sources in different working state
 Supports 7 separate voltage domains
 Supports 30 separate power domains, which can be power up/down by software
based on different application scenes
 Timer
 Supports 12 secure timers with 64bits counter and interrupt-based operation
 Supports 18 non-secure timers with 64bits counter and interrupt-based operation
 Supports two operation modes: free-running and user-defined count for each timer
 Supports timer work state checkable

RK3576、RK3576J、RK3576M套片&开发板&核心板

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