void BSP_SetSysClk(void)
{
stc_clock_xtal_init_t stcXtalInit;
stc_clock_pll_init_t stcPLLHInit;
stc_pll_clock_freq_t pstcPllClkFreq;
stc_clock_freq_t pstcClockFreq;
stc_clock_scale_t clk_freq_cfg;
/* Config Xtal and enable Xtal */
stcXtalInit.u8Mode = CLK_XTAL_MD_OSC;
stcXtalInit.u8Drv = CLK_XTAL_DRV_LOW;
stcXtalInit.u8State = CLK_XTAL_ON;
stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS;
CLK_XtalInit( &stcXtalInit );
CLK_XtalCmd(ENABLE);
/* VCO = (8/1)*120 = 960MHz*/
stcPLLHInit.u8PLLState = CLK_PLL_ON;
stcPLLHInit.PLLCFGR = 0UL;
stcPLLHInit.PLLCFGR_f.PLLM = 1UL-1UL;
stcPLLHInit.PLLCFGR_f.PLLN = 120UL-1UL;
stcPLLHInit.PLLCFGR_f.PLLP = 4UL-1UL;
stcPLLHInit.PLLCFGR_f.PLLQ = 4UL-1UL;
stcPLLHInit.PLLCFGR_f.PLLR = 4UL-1UL;
stcPLLHInit.PLLCFGR_f.PLLSRC = CLK_PLL_SRC_XTAL;
CLK_PLLInit( &stcPLLHInit );
/* flash read wait cycle setting */
EFM_REG_Unlock();
EFM_SetWaitCycle(EFM_WAIT_CYCLE1);
EFM_REG_Lock();
CLK_PLLCmd(ENABLE);
/* Wait MPLL ready. */
//while (SET != CLK_GetStableStatus(CLK_STB_FLAG_PLL)){}
CLK_SetSysClockSrc( CLK_SYSCLK_SRC_PLL );
}
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