以下的代码，老是通不过编译，显示的错误是：Error (10822): HDL error at test17.vhd(384): couldn't implement registers for assignments on this clock edge
这段代码的主要意思是当speed2有下降沿时，通过外部时钟开始计数，等到“11111111”时间后，如果speed2还是低电平，则给计数器result加1，否则不加。主要是防止信号误操作的。
请各位大侠帮忙看看，是顺序有问题，还是哪里 有问题。谢谢
test:process(speed2,EXTCLK)
begin
case speedtest3 is
when 0 =>
if speed2'event and speed2='0'then
m<='1';
end if;
when 1 =>
result1<=result;
result<="0000000000000000";
end case;
if(m<='1')then
if EXTCLK'event and EXTCLK='1'then
if counter100="11111111" then
if(speed2<='0')then
result<=result+1;
counter100<="00000000";
m<='0';
else m<='0';
counter100<="00000000";
end if;
else
counter100<=counter100+1;
end if;
end if;
end if;
end process;
commu:process (Tclk1)
begin
if tclk1'event and tclk1='1'then
if counter1000="100111000100000"then
int_t(3)<='0';
en_serial<='1';
counter1000<="00000000000000";
else counter1000<=counter1000+1;
int_t(3)<='1';
end if;
end if;
if (en_serial='1')then
result1<=result;
clear<='1';
en_serial<='0';
end if;
if (clear='1') then result<="0000000000000000";
clear<='0';
else
--if speed2'event and speed2='0'then
if c='0'and d='1'then
if a='0'and b='1'then
if counter100="11111111"then
result<=result+1;
counter100<="00000000";
else counter100<=counter100+1;
end if;
end if;
end if;
end if;
end process;
commu:process (Tclk1)
begin
if tclk1'event and tclk1='1'then
if counter1000="10011011010100"then
int_t(3)<='0';
en_serial<='1';
counter1000<="00000000000000";
else counter1000<=counter1000+1;
int_t(3)<='1';
end if;
end if;
if (en_serial='1')then
result1<=result;
clear<='1';
en_serial<='0';
end if;
if (clear='1') then result<="0000000000000000";
clear<='0';
else
if c='0'and d='1'then
result<=result+1;
end if;
end if;
我要疯了，估计你也差不多了吧，我写了一个小程序来测试，可是居然也没法计数：
test1:process(tclk1)
begin
if TCLK1'event and TCLK1='1'then
c<=speed2;
d<=c;
end if;
if c='0'and d='1'then
e<=not e;
speed1<=e;
end if;
end process;
楼主
