本帖最后由 hust_lilinbing 于 2012-7-25 21:24 编辑
模块flopmodule flop(data,clock,clear,q,qb); input data,clock,clear; output q,qb; nand #10 nd1(a,data,clock,clear), nd2(b,ndata,clock), nd4(d,c,b,clear), nd5(e,c,nclock), nd6(f,d,nclock), nd8(qb,q,f,clear); nand #9 nd3(c,a,d), nd7(q,e,qb); not #10 iv1(ndata,data), iv2(nclock,clock);endmodule 模块hardreg`include "flop.v"module hardreg(d,clk,clrb,q);input clk,clrb;input[3:0] d;output[3:0] q;flop f1(d[0],clk,clrb,q[0],), f2(d[1],clk,clrb,q[1],), f3(d[2],clk,clrb,q[2],), f4(d[3],clk,clrb,q[3],);endmodule 错误提示：Error (10054): Verilog HDL File I/O error at hardreg.v(1): can't open Verilog Design File "flop.v"Error (10112): Ignored design unit "hardreg" at hardreg.v(2) due to previous errorsError: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 5 warnings Error: Peak virtual memory: 210 megabytes Error: Processing ended: Tue Jul 24 23:13:44 2012 Error: Elapsed time: 00:00:01 Error: Total CPU time (on all processors): 00:00:01Error: Quartus II Full Compilation was unsuccessful. 4 errors, 5 warnings注：模块flop和模块hardreg不在一个文件夹里。 |
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