【高手指点】vhdl 进程嵌套循环过程
在进程中嵌套循环过程的语法问题，代码如下：
procedure (signal c : integer;
signal d : integer ) is
begin
......(省略)
end procedure;
type ArrayNxInt is array (natural range <>) of Integer;
signal a :ArrayNxInt (0 to 1);
signal b :ArrayNxInt (0 to 1);
process (clk)
begin
if (clk'event and clk = '1') then
for i in 0 to 1 loop
Procedure1 (a(i), b(i));
end loop;
end if;
end process;
modelsim仿真是报错：
Actual (indexed name) for formal "c" is not a static signal;
Actual (indexed name) for formal "d" is not a static signal;
如果代码改为
process (clk)
begin
if (clk'event and clk = '1') then
Procedure1 (a(0), b(0));
Procedure1 (a(1), b(1));
end if;
end process;
或者组合逻辑
Label1 : for i in 0 to 1 generate
Procedure1 (a(i), b(i));
end generate;
就没有问题。
在process中，编译器好像不能正确翻译for循环+进程语句。
现在需要在process中调用procedure，并且需要for循环，请高手指点，多谢！ |
楼主
