Verilog HDL应用程序设计实例精讲
这本书里面的1个例子
//异步清零输入的下降沿D触发器
module test1(q,d,clr,clk);
input d,clr,clk;
output q;
reg q;//输出,寄存器类型
always @(clr)//清零信号
begin
if(!clr)//下降沿清零
assign q = 0;
else
deassign q;
end
always @(negedge clk)//下降沿时钟
begin
q = d;
end
endmodule
编译失败了.
Error (10043): Verilog HDL unsupported feature error at test1.v(11): Procedural Continuous Assignment to register is not supported |