Verilog语言实现流水线设计全加器

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楼主 | 2012-10-8 22:05 | 只看该作者回帖奖励

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Verilog语言, npu, Input, TI, IO

Verilog语言实现流水线设计四位全加器，在此举例说明流水线算法的思想
module  add4v(a,b,ci,s,co);
input[3:0] a;
input[3:0] b;
input  ci;
output[3:0] s;
output co;

wire[3:0] carry;

function fa_s(input a,input b,input ci);
   fa_s  = a ^ b ^ ci;
endfunction

function fa_c(input a,input b,input ci);
   fa_c = a & b | a & ci | b & ci;
endfunction

assign  s[0]    = fa_s(a[0],b[0],ci);
assign  carry[0] = fa_c(a[0],b[0],ci);

assign  s[1]    = fa_s(a[1],b[1],carry[0]);
assign  carry[1] = fa_c(a[1],b[1],carry[0]);

assign  s[2]    = fa_s(a[2],b[2],carry[1]);
assign  carry[2] = fa_c(a[2],b[2],carry[1]);

assign  s[3]    = fa_s(a[3],b[3],carry[2]);
assign  co    = fa_c(a[3],b[3],carry[2]);
endmodule
以下内容为testbench
module  add4v_tb;
  reg[3:0]  a;
  reg[3:0]  b;
  reg ci;
  wire[3:0] s;
  wire co;

  add4v  ut(a,b,ci,s,co);
  initial  begin
   a = 0;
   b = 0;
   ci  = 0;
end
always #50  a  = a + 1;
always #100 b  = a + 1;
endmodule

使用特权