To Associate ELF Files with Embedded Processors in the ISE Design
In Project Navigator, ELF files that are associated with the processors in XPS automatically appear under the XMP file in the Hierarchy pane of the Design panel. You can add the ELF files to the project and associate them with individual processors in the XMP source file as follows:
- Select Project > Add Source.
- In the Add Source dialog box, select the ELF file, and click Open.
- In the Adding Source dialog box, specify the Design View Association, whether Implementation, Simulation, or All, and click OK. For more information, see Using the Design Views.
- In theELF/XMP File Associations dialog box, select the processor instance to associate with the ELF file, and click OK.
- （要说明的一点是：elf文件在你的xps文件中的empty_application_0\debuge中）。
Note After the ELF files are added to the project, you can view or modify file associations from the Hierarchy pane. Right-click an ELF file, and select Elf/Xmp File Associations to open the ELF/XMP File Associations dialog box. Alternatively, right-click an XMP file, and select Xmp/Elf File Associations to open the XMP/ELF File Associations dialog box.
To Simulate the Embedded Processor System
If the XMP source files are instantiated as lower-level modules in your ISE design, you can simulate the design normally, as described in the Simulation Overview, and the Project Navigator and EDK software automatically generate the simulation files necessary for simulating your embedded processor system.
You can use the Generate HDL Test Bench (XPS) process to create a template test bench for the XMP embedded processor module. You can then do either of the following:
- Use this test bench directly to simulate the embedded processor module.
- Copy the test bench contents into a higher level design test bench, and modify the paths to simulate the embedded processor module as part of the larger design.
Note The XMP module cannot be simulated directly. It must be instantiated directly in a test bench or instantiated as part of a larger design.
To Implement the Embedded Processor System
After you instantiate the XMP source files as lower-level modules in your ISE design, you can implement your design as described in Implementation Overview for FPGAs. After implementation, the embedded processor system is included in the placed and routed design.
Following are additional details regarding implementation behavior:
- Synthesis and implementation options are not shared between XPS and Project Navigator.Note When setting Map Properties in Project Navigator, Xilinx recommends that you set the Map Effort Level to High when working with an embedded processor system.
- Process status becomes out-of date in the Processes pane of the Design panel if you modify your embedded processor system in XPS. For example, changes to the MHS file cause the Synthesis and Implement Design processes to become out-of-date. Changes to the User Constraints File (UCF) cause the Implement Design process to become out-of-date. For more information on process status, seeRunning and Stopping Processes.
- Constraints generated in XPS (for the system module as well as instantiated embedded IP) are automatically copied into the ISE project directory as NCF files and are picked up automatically when you implement your design. If you need to modify the constraints associated with the embedded processor system, you must modify the constraints in XPS.
Note For more information, see Copying Constraints to Your ISE Project in the XPS Help.
To View Implementation Results Data
The Project Navigator Design Summary provides access to ISE synthesis and implementation reports and messages as well as XPS reports and messages from the PlatGen, LibGen, SimGen and BitInit programs. For more information, see the Design Summary Overview.
To Generate a Bitstream File with Processor Data
To generate a bitstream file with processor data, run the Generate Programming File process. This process generates the bitstream for the hardware components of the FPGA device, including the software application data from the ELF files that are part of the project.
To Export the Hardware Design to SDK
For embedded software development, the XPS hardware description must be exported to the Software Development Kit (SDK). You can export just the hardware description file without the bitstream and BMM files, or you can export the hardware description file with the bitstream and BMM files. For more information, see Exporting a Hardware Design to SDK.
See Also
Intellectual Property and Cores Overview
二、要进行生成xps的顶层文件：
三、声明和例化xps文件到顶层
COMPONENT system
PORT(
fpga_0_RS232_PORT_RX_pin : IN std_logic;
fpga_0_clk_1_sys_clk_pin : IN std_logic;
fpga_0_rst_1_sys_rst_pin : IN std_logic;
ps_ip_0_PS2CLK_pin : IN std_logic;
ps_ip_0_PS2DATA_pin : IN std_logic;
fpga_0_RS232_PORT_TX_pin : OUT std_logic;
ps_ip_0_DATA_pin : OUT std_logic_vector(0 to 15)
);
END COMPONENT;
attribute box_type : string;
attribute box_type of system : component is "user_black_box";
例化：
Inst_system: system PORT MAP(
fpga_0_RS232_PORT_RX_pin => fpga_0_RS232_PORT_RX_pin,
fpga_0_RS232_PORT_TX_pin => fpga_0_RS232_PORT_TX_pin,
fpga_0_clk_1_sys_clk_pin => clk,
fpga_0_rst_1_sys_rst_pin => fpga_0_rst_1_sys_rst_pin,
ps_ip_0_PS2CLK_pin => ps_ip_0_PS2CLK_pin,
ps_ip_0_PS2DATA_pin => ps_ip_0_PS2DATA_pin,
ps_ip_0_DATA_pin => x
);
在端口声明中要添加
fpga_0_rst_1_sys_rst_pin : IN std_logic;--注意：在edk中fpga_0_rst_1_sys_rst_pin为高电平时复位，在ise中低电平复位
ps_ip_0_PS2CLK_pin : in std_logic;
ps_ip_0_PS2DATA_pin : in std_logic;
fpga_0_RS232_PORT_RX_pin :in std_logic;
fpga_0_RS232_PORT_TX_pin : out std_logic;
四、ucf文件的问题
edk中已经添加了 在你add source时已经添加到user constraints管理器中了，所以不用在添加，因为是在ise中，要更改电平为3.3v和xps一致，否则出错！
五、对于在ise和edk之间通信的信号应该如何定义的问题
在本实验中使用的是data数据也就是ise中的 ps_ip_0_PS2DATA_pin，你只需要在xps中port目录下将其连接为make external，
ucf文件配置就不用了。别忘了在mpd、use_logic、ps_ip文件中配置data为输出端口奥！
六、user_logic中的注意事项
（一）
data <=slv_reg0(16 to 31)；--在plb总线协议中数据是从高位开始读取的
c语言中是这样写的
# include
# include
# include
main()
{
u32 i;
// char i;
unsigned long j;
while(1)
{
//PS_IP_SelfTest(XPAR_PS_IP_0_BASEADDR);
i=PS_IP_mReadSlaveReg0(XPAR_PS_IP_0_BASEADDR, 0);//键盘值读取
PS_IP_mWriteSlaveReg0(XPAR_PS_IP_0_BASEADDR, 0,i);//返回数据到slv——reg0再到ise，在数码管上显示
xil_printf("zhi : %x \r\n",i); //通过串口打印
// for(j=0;j<=9999999;j++);
}
}
（二）
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1 ) is
begin
case slv_reg_read_sel is
when "10" => slv_ip2bus_data <=shift1(8 downto 1) & shift2(8 downto 1);--slv_reg0;
when "01" => slv_ip2bus_data <= slv_reg1;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
我把他换成了直接赋值，原因是当输入和输出共用时，slv_reg0出现了报错，具有多个驱动
多交流！ |
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