This is an explanation on how the FlashBurn utility works, and how the FlashBurn Porting Kit is used to support custom flash configurations.
Code Composer Studio, FlashBurn, and the FBTC Program The following diagram shows how FlashBurn works together with Code Composer Studio to program flash.
Key Points:
FlashBurn uses Code Composer Studio for all communication to the target hardware. This requires a JTAG emulator or the on-board communication present on the DSK boards.
FlashBurn begins by downloading a small target application called the FlashBurn Target Component (FBTC) to the RAM on the target hardware. The FBTC implements all of the capability to erase, program and verify flash memory on the target.
FlashBurn starts the FBTC program running on the target hardware and begin communicating with it over the JTAG connection.
FlashBurn reads the flash image to be programmed from a .hex file. The flash image is sent to the running FBTC program over JTAG using Code Composer Studio.
The running FBTC program burns the flash image into Flash memory.
Using the FlashBurn Porting Kit The FlashBurn DSK product delivers flash programming support a predefined set of TI DSK boards. In order to support custom hardware with different Flash devices or memory configurations, the FBTC program must be modified using the FlashBurn Kit.
The FlashBurn Porting Kit consists of:
Complete C source code for the FBTC programs that implement flash programming on each of the DSKs supported in the FlashBurn DSK product. This gives running examples of FBTC programs for C54x, C55x, C64x, C67x and OMAP 5912.
A FlashBurn Programmers Reference that describes the porting process.
The porting process normally consists of:
Choosing an example FBTC program that closely matches the desired hardware configuration .
Modifying the FBTC program to correctly erase, program and, verify the flash contents.
Persons performing the FBTC port should be familiar with:
The DSP architecture and use of Code Composer Studio to build and debug their custom FBTC program
Board initialization, chip enables, and memory configuration concerns specific to the new target hardware