本帖最后由 lanpad 于 2012-10-28 21:23 编辑
芯片是xilinx的XC6SLX9
用了DCM模块倍频
发现倍频输出后的时钟不能用
看了很多资料，说是要加一个叫“ODDR2”的东西
加上去之后又产生了新的错误：
ERROR:Pack:2531 - The dual data rate register "U_ODDR2_clk200M" failed to join
the "OLOGIC2" component as required. The output signal for register symbol
U_ODDR2_clk200M requires general routing to fabric, but the register can only
be routed to ILOGIC, IODELAY, and IOB.
源代码如下：
module XXXXX(
clk10M,
rst,
sig_1,
sig_2,
clk200M_out,
.......
........
);
input clk10M;
input rst;
input sig_1;
input sig_2;
output clk200M_out;
.........
.........
wire clk200M;
wire clk200M_out;
clk_dcm Unit1(//倍频模块
.CLK_IN1(clk10M),
.RESET(rst),
.CLK_OUT1(clk200M),
.LOCKED(clk_lock)
);
ODDR2 #(
.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
) U_ODDR2_clk200M
(
.Q(clk200M_out), // 1-bit DDR output data
.C0(clk200M), // 1-bit clock input
.C1(~clk200M), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D0(1'b1), // 1-bit data input (associated with C0)
.D1(1'b0), // 1-bit data input (associated with C1)
.R(1'b0), // 1-bit reset input
.S(1'b0) // 1-bit set input
);
XXXXX Unit2(
.clk(clk200M_out),
.clk_com(clk_com),
.rst(rst),
.d(XX)
);
com_t Unit3(//串口输出模块
.reset(rst),
.clk16x(clk_com),
.din(dout),
.wrn(comt_en),
.com1_sdo(PF_out)
);
clk_div Unit4(//串口时钟产生模块
.rst(rst),
.clk(clk200M_out),/
.clk_com(clk_com)
);
endmodule
谁能帮忙看看怎么回事？
谢谢了！ |
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