关于 SCK 的频率, 手册上有这么一段话.
3.2 SCLK Input
The SCLK (serial clock) is used as the conversion clock to shift out the conversion result. SCLK is TTL and CMOS compatible. Internal settling time requirements limit the maximum clock frequency while internal capacitor leakage limits the minimum clock frequency. The ADC141S626 offers guaranteed performance with the clock rates indicated in the electrical table.
The ADC141S626 enters acquisition mode on the 16th falling edge of SCLK during a conversion frame. Assuming that the LSB is clocked into a controller on the 16th rising edge of SCLK, there is a minimum acquisition time period that must be met before a new conversion frame can begin. Other than the 16th rising edge of SCLK that was used to latch the LSB into a controller, there is no requirement for the SCLK to transition during acquisition mode. Therefore, it is acceptable to idle SCLK after the LSB has been latched into the controller.
总的说来, 是由器件内部的一些参数导致的限制. 为了它工作得可靠, 还是遵守它的规定吧.
楼主比较较真哪, 我只是从手册上看:
Internal settling time requirements limit the maximum clock frequency while internal capacitor leakage limits the minimum clock frequency.
频率过低, 可能输出不稳定.
如果,时钟的高低脉冲时间不对称, 我认为允许的频率范围可能会更窄
实际经验我没有, 也没有这个条件去试验.
楼主可以自己做个测试, 事实上, 这类数据一般都比较保守的. 可能要偏出很多才会真的出现异常.
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