请教Cypress 68013 IFCLK不输出原因

只看该作者 · 2012-11-4 14:42

用的128Pin 芯片，把IFCONFIG b7 b5都配成1，发现IFCLK死活不出来。
是不是还需要啥特殊的配置。

那位高手分析下可能的原因。

只看该作者 · 2012-11-4 15:35

枚举没啥问题,程序也可以跑,说明内部时钟都是好的。

把Init代码贴一下：
void TD_Init(void)          // Called once at startup
{
  CPUCS = 0x12; // CLKSPD[1:0]=10, for 48MHz operation, output CLKOUT

  //FIFOPINPOLAR |= 0x03;

  PINFLAGSAB = 0x08; // FLAGA - EP2EF // Flag B an C indexed
  SYNCDELAY;
  PINFLAGSCD = 0x0e; // FLAGD - EP6FF
  SYNCDELAY;
// PORTACFG |= 0x80;
  IFCONFIG = 0xE3; // for async? for sync? 1100 1011
  SYNCDELAY;

PORTACFG |= 0x80;

// EP4 and EP8 are not used in this implementation...

  EP2CFG = 0xA0;             //out 512 bytes, 4x, bulk
  SYNCDELAY;
  EP6CFG = 0xE0;             // in 512 bytes, 4x, bulk
  SYNCDELAY;
  EP4CFG = 0x02;             //clear valid bit
  SYNCDELAY;
  EP8CFG = 0x02;             //clear valid bit
  SYNCDELAY;

  SYNCDELAY;
  FIFORESET = 0x80;          // activate NAK-ALL to avoid race conditions
  SYNCDELAY;                   // see TRM section 15.14
  FIFORESET = 0x02;          // reset, FIFO 2
  SYNCDELAY;                   //
  FIFORESET = 0x04;          // reset, FIFO 4
  SYNCDELAY;                   //
  FIFORESET = 0x06;          // reset, FIFO 6
  SYNCDELAY;                   //
  FIFORESET = 0x08;          // reset, FIFO 8
  SYNCDELAY;                   //
  FIFORESET = 0x00;          // deactivate NAK-ALL

  // handle the case where we were already in AUTO mode...
  // ...for example: back to back firmware downloads...
  SYNCDELAY;                   //
  EP2FIFOCFG = 0x00;          // AUTOOUT=0, WORDWIDE=1

  // core needs to see AUTOOUT=0 to AUTOOUT=1 switch to arm endp's

  SYNCDELAY;                   //
  EP2FIFOCFG = 0x10;          // AUTOOUT=1, WORDWIDE=1

  SYNCDELAY;                   //
  EP6FIFOCFG = 0x4C;          // AUTOIN=0, ZEROLENIN=1, WORDWIDE=1
  // EP6FIFOCFG = 0x4E
// I have made some modification here to make it testable without FPGA
  // 6 INFM1 IN Full Minus One.
  // 5 OEP1 OUT Empty Plus One.
  // 4 AUTOOUT Instantaneous Connection to Endpoint FIFO. This bit applies only to OUT endpoints.
  // 3 AUTOIN Auto Commit to SIE. This bit applies only to IN endpoints.  !!  auto in slave fifo mode
  // 2 ZEROLENIN Enable Zero length IN Packets.
  // 0 WORDWIDE Select Byte/Word FIFOs on PORTB/D Pins.
  SYNCDELAY;
}

只看该作者 · 2012-11-4 17:09

试了试CLKOUT可以输出，今天先到这里，明天再来查错了

只看该作者 · 2012-11-7 22:20

今天终于查清原因了，原来是RESERVED pin没有接地。第一次用这块芯片，看来真是交学费了。

只看该作者 · 2012-11-7 22:24

这个Reserved pin 官方给的解释是：
The RESERVED pin is a test mode pin. If it is not grounded, the FX2LP is placed into a test mode and does not operate correctly.

datasheet和TRM里面都没写，是不是有点坑爹。。。

请教Cypress 68013 IFCLK不输出原因

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