--************************************************************
-- widthDAT 数据的位宽 ; widthRF 为旋转因子的位宽
-- 实现了一个复数和旋转因子的相乘操作 yi+yq*j=(xi+xq*j)*(cos-sin*j)
--************************************************************
-- 修改ccmul，使与旋转因子相乘后数据的位数不发生变化 2007.11.24
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
library lpm;
use lpm.lpm_components.all;
use work.mypackage.all;
-- This entity has an attentuation of 1 bits.
-- This entity has a delay of 2 clock cycles.
entity ccmul is
generic(widthDAT:NATURAL:=16; widthRF :NATURAL:=16);
port(
clk :in std_logic;
enable :in std_logic;
cos ,sin :in std_logic_vector(widthRF-1 downto 0);
X :in std_logic_vector(2*widthDAT-1 downto 0); -- 输入复数
Y :out std_logic_vector(2*widthDAT-1 downto 0));
end ccmul;
architecture rtl of ccmul is
constant widthMUL : NATURAL := widthRF+widthDAT;
signal xi,xq :std_logic_vector(widthDAT-1 downto 0); -- 两级加法扩展2位
signal cos_reg,sin_reg:std_logic_vector(widthRF-1 downto 0);
signal xic,xqs,xqc,xis:std_logic_vector(widthMUL-1 downto 0);
signal xich,xqsh,xqch,xish:std_logic_vector(widthDAT-1 downto 0);
signal enable0,enable1:std_logic;
begin
rrmul1:lpm_mult
generic map(lpm_widtha=>widthDAT,lpm_widthb=>widthRF,
lpm_widthp=>widthMUL,lpm_widths=>1,
lpm_representation=>"signed")
port map(dataa=>xi,datab=>cos_reg,result=>xic);
rrmul2:lpm_mult
generic map(lpm_widtha=>widthDAT,lpm_widthb=>widthRF,
lpm_widthp=>widthMUL,lpm_widths=>1,
lpm_representation=>"signed")
port map(dataa=>xq,datab=>sin_reg,result=>xqs);
rrmul3:lpm_mult
generic map(lpm_widtha=>widthDAT,lpm_widthb=>widthRF,
lpm_widthp=>widthMUL,lpm_widths=>1,
lpm_representation=>"signed")
port map(dataa=>xq,datab=>cos_reg,result=>xqc);
rrmul4:lpm_mult
generic map(lpm_widtha=>widthDAT,lpm_widthb=>widthRF,
lpm_widthp=>widthMUL,lpm_widths=>1,
lpm_representation=>"signed")
port map(dataa=>xi,datab=>sin_reg,result=>xis);
process(clk)
begin
if(clk'event and clk='1')then
if(enable='1')then
xi <= X(2*widthDAT-1 downto widthDAT);
xq <= X(widthDAT-1 downto 0);
sin_reg <= sin; cos_reg <= cos;
end if;
end if;
end process;
process
begin
enable0 <= enable;
-- enable1 <= enable0;
wait until clk='1';
end process;
--process(clk)
--begin
--if(clk'event and clk='1')then
--if(enable0='1')then
xich <=xic(widthMUL-1 downto widthRF);
xqsh <=xqs(widthMUL-1 downto widthRF);
xqch <=xqc(widthMUL-1 downto widthRF);
xish <=xis(widthMUL-1 downto widthRF);
--end if;
--end if;
--end process;
process(clk)
begin
if(clk'event and clk='1')then
--if(enable0='1')then
Y(2*widthDAT-1 downto widthDAT) <= signed_add(xich,xqsh);
Y(widthDAT-1 downto 0) <= signed_sub(xqch,xish);
--end if;
end if;
end process;
本文来自：我爱研发网(52RD.com) - R&D大本营
详细出处：http://www.52rd.com/Blog/Archive_Thread.asp?SID=11833 |
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