module Filter(
input wire clk,
input wire rst_n,
input wire A,
output wire AF
);
reg A_R1,A_R2,A_R3;
wire A_And_Not, A_Or_Not;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
A_R1 <= 1'b0;
A_R2 <= 1'b0;
A_R3 <= 1'b0;
end
else begin
A_R1 <= A;
A_R2 <= A_R1;
A_R3 <= A_R2;
end
end
assign A_And_Not = ~(A_R1 & A_R2 & A_R3);
assign A_Or_Not = ~(A_R1 | A_R2 | A_R3);
//using negedge of clk
JKFF74LS109 JKFF74LS109_AInst(
.clk(~clk),
.J(A_Or_Not),
.K_Bar(A_And_Not),
.Q(),
.Q_Bar(AF));
endmodule
//implement a J-K Flipflop, and the behavior model is from 74LS109 chip
module JKFF74LS109(
input wire clk,
input wire J,
input wire K_Bar,
output reg Q,
output wire Q_Bar);
assign Q_Bar = ~Q;
always @(posedge clk) begin
case ({J, K_Bar})
2'b00: Q <= 1'b0;
2'b10: Q <= ~Q;
2'b01: Q <= Q;
2'b11: Q <= 1'b1;
default: Q <= 1'bx;
endcase
end
endmodule
这是消除毛刺的，我不是很理解，谁能帮我讲解一下 |
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