library ieee;
use ieee.std_logic_1164.all;
entity lq123 is
port(
a : in integer range 0 to 15;
din : in std_logic_vector(7 downto 0);
dout: out std_logic_vector(7 downto 0);
clk,cs,we,ce:in std_logic );
end entity lq123;
architecture one of lq123 is
type ram_type is array (0 to 15)of std_logic_vector(7 downto 0);
begin
process(clk,a,din,cs,we,ce)is
variable mem:ram_type;
begin
if clk'event and clk ='1'then
dout <=(others => 'Z');
if cs ='0'then
if ce='0'then
dout <= mem(a);
elsif we='0'then
mem(a):=din;
end if;
end if;
end if ;
end process;
end one; |
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