代码如下
module ram( dataout, addr, wr, rd, cs, datain );
output[7:0] dataout;
input[4:0] addr;
input[7:0] datain;
input cs, wr, rd;
reg[7:0] datastore[31:0];
reg[7:0] dataout;
//write data
always @ ( wr, cs, addr, datastore, datain )
begin
if( cs == 0 )
begin
if( wr )
begin
datastore[addr] = datain;
end
else
begin
dataout = 8'bz;
end
end
end
//read data
always @ ( rd, cs, addr, datastore )
begin
if( cs == 0 )
begin
if( rd )
begin
dataout = datastore[addr];
end
else
begin
dataout = 8'bz;
end
end
end
endmodule |
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