给程序挑错

只看该作者 · 2012-12-30 19:40

library IEEE ;
use IEEE.std_logic_1164.all ;
use IEEE.std_logic_unsigned.all ;
use IEEE.numeric_std.all ;

entity key1 is
port ( Clk_I : in std_logic ;
      Rst_I : in std_logic ;
      key_I : in std_logic ;
      key_O : out std_logic );
end entity ;
architecture rt1 of key1 is
type state_type is (s0, s1, s2, s3, s4, s5);
signal state    : state_type ;
signal count    : integer range 0 to 80000 ;
signal reg    : std_logic ;
signal key_confirm : std_logic ;
begin
reg <= key_I ;
  process (Clk_I, Rst_I)
begin
   if Rst_I = '0' then
            state <= s0 ;
   elsif Clk_I'event and Clk_I = '1' then

      case state is
            when s0 => if reg = '1' then
                           state <= s0;
                        else state <= s1;
                        end if ;
            when s1 => if count = 80000 then
                           count <= 0 ;
                           state <= s2 ;
                        else count <= count + 1 ;
                           state <= s1 ;
                        end if ;
            when s2 => if reg = '1' then
                           state <= s0 ;
                        else state <= s3;
                        end if ;
            when s3 => if reg = '1' then
                           state <= s0 ;
                        else state <= s4 ;
                        end if ;
            when s4 => if reg = '1' then
                           state <= s0 ;
                        else state <= s5 ;
                        end if ;
            when s5 => if reg ='0' then
                           state <= s0 ;
                        else state <= s5 ;
                        end if ;
            when others => state <= s0 ;
         end case ;
   end if ;
end process ;
process (Clk_I)
   begin
   if Clk_I'event and Clk_I = '1' then
      case state is
         when s5 => key_confirm <= '1' ;
         when others => key_confirm <= '0' ;
      end case ;
      end if ;
   end process ;
key_O <= key_confirm ;
end rt1;