VHDL这么写，有什么错？
LED1，LED2，LED3是输出端口。
LED1 : out std_logic;
LED2 : out std_logic;
LED3 : out std_logic;
RecData: Process
begin
TagRecData(3 downto 0) <= axi_gpio_0_GPIO_IO_O_pin(30 downto 27);
--the data is should be judeged suitable.
if(TagRecData = "0001" ) then
LED1 <= '0';
LED2 <= '1';
LED3 <= '1';
else if (TagRecData = "0010" ) then
LED1 <= '0';
LED2 <= '0';
LED3 <= '1';
else if (TagRecData = "0011" ) then
LED1 <= '1';
LED2 <= '0';
LED3 <= '1';
else
null;
end if;
end process RecData;
还没编译，保存后就出现错误，Syntax error near "process".把if部分屏蔽就好了，请问为何？
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楼主
