摘自Prentice Hall - Signal Integrity Simplified：
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Appendix A. 100 General Design Guidelines to Minimize Signal-Integrity Problems
Never follow a rule blindly. Always understand its purpose and put in the numbers to evaluate its cost/benefit for your specific design.
0. Always use the longest rise time you can.
A.1 Minimize Signal-Quality Problems on One Net
Strategy: Keep the instantaneous impedance the signal sees constant throughout its entire path.
Tactics:
1.Use controlled-impedance traces.
2.Ideally, all signals should use the low-voltage planes as their reference planes.
3.If different voltage planes are used as signal references, there should be tight coupling between them. Do so by using the thinnest dielectric you can afford and multiple, low-inductance decoupling capacitors between the different voltage planes.
4.Use a 2D field solver to calculate the stack-up design rules for the target characteristic impedance. Include the effects of solder-mask and trace thickness.
5.Use series termination for point-to-point topologies, whether single or bidirectional.
6.Terminate both ends of the buss in a multidrop bus.
7.Keep the time delay of stubs less than 20% of the rise time of the fastest signals.
8.Place the terminating resistors as close to the package pads as possible.
9.Don't worry about corners unless 10 fF of capacitance is important.
10.Follow the return path of each signal and keep the width of the return path under each signal path at least as wide, and preferably at least 3 times as wide, as the signal trace.
11.Route signal traces around rather than across return-path discontinuities.
12.Avoid using engineering change wires in any signal path.
13.Keep all nonuniform regions as short as possible.
14.Do not use axial-lead terminating resistors for system rise times less than 1 nsec. Use SMT resistors and mount them for minimum loop inductance.
15.When rise times are less than 150 psec, do everything possible to minimize the loop inductance of the terminating SMT resistors or consider using integrated or embedded resistors.
16.Vias generally look capacitive. Minimizing the capture pads and increasing the antipad clearance diameter will help make the via look transparent.
17.Consider adding a little capacitance to the pads of a low-cost connector to compensate for its typically higher inductance.
18.Route all differential pairs with a constant differential impedance.
19.Avoid all asymmetries in a differential pair. Whatever you do to one trace, do the same to the other.
20.If the spacing between the traces in a differential pair has to change, adjust the line width to keep a constant differential impedance.
21.If a delay line is to be added to one leg of a differential pair, add it near the beginning of the trace and keep the traces uncoupled in this region.
22.It is okay to change the coupling in a differential pair as long as the differential impedance is maintained.
23.In general, route differential-pair traces with as tight a coupling as practical.
24.Decide on edge- versus broadside-coupled differential pairs, based on routing density, total board-thickness constraints, and ability of the fab vendor to maintain tight laminate thickness control. Performance wise, they can be equivalent.
25.For any board-level differential pairs, there will be significant return current in the planes, so avoid all discontinuities in the return path. If there is a discontinuity, do exactly the same thing to each line in the pair.
26.Worry about terminating the common signals only if the common-mode rejection ratio of the receiver is poor. Terminating the common signals will not eliminate the common signal, just minimize its ringing.
27.If losses are important, use as wide a signal trace as possible, and never use a trace of less than 5 mils.
28.If losses are important, keep traces as short as possible.
29.If losses are important, do everything possible to minimize all capacitive discontinuities.
30.If losses are important, engineer the signal-vias to have a 50-Ohm impedance, which usually means do everything possible to decrease the barrel size, decrease the capture-pad size, and increase the antipad-clearance holes.
31.If losses are important, use as low a dissipation-factor laminate as you can afford.
32.Consider using pre-emphasis and equalization if losses are important.
A.2 Minimize Cross Talk
Strategy: Minimize mutual capacitance and mutual inductance between signal and return paths.
Tactics:
33.For microstrip or stripline transmission lines, keep the spacing between adjacent signal paths at least twice the line width.
34.Minimize any discontinuities in the return path the signals might cross over.
35.If you have to cross a gap in the return path, only use differential pairs. Never cross a gap with single-ended signals routed close together.
36.For surface traces, keep the coupled lengths as short as possible and use as much solder mask as practical to minimize far-end cross talk.
37.If far-end cross talk is a problem, add a laminate layer to the top of the surface traces to make them embedded microstrip.
38.For long, coupled lengths where far-end cross talk may be a problem, route the traces in stripline.
39.If you can't keep the coupling length less than the saturation length, changing the coupling length will have no impact on the near-end cross talk, so don't worry about decreasing coupling length.
40.Use the lowest dielectric constant laminate you can afford so the dielectric spacing to the return planes can be kept to a minimum for the same target characteristic impedance.
41.In a tightly coupled microstrip bus, the deterministic jitter can be reduced by keeping the spacing at least as wide as twice the line width or by routing timing-sensitive lines in stripline.
42.For isolations in excess of –60 dB, use stripline with guard traces.
43.Always use a 2D field solver to evaluate whether you need to use a guard trace.
44.If you do use a guard trace, make it as wide as will fit and use vias to short the ends to the return path. Add additional shorting vias along the length if it is free and easy to do so. They are not as critical as the two on the ends.
45.Minimize ground bounce by making the return paths in any packages or connectors as short and as wide as possible.
46.Use chip-scale packages rather than larger packages.
47.Minimize ground bounce in the power return path by bringing the power plane as close to the return plane as possible.
48.Minimize ground bounce in the signal return paths by bringing the signal path as close to the return path as acceptable, consistent with matching the impedance of the system.
49.Avoid using shared return paths in connectors and packages.
50.When assigning leads in a package or connector, reserve the shortest leads for the ground paths and space the power and ground leads uniformly among the signal paths, or closest to those signal paths that will carry a lot of switching current.
51.All no-connect leads or pins should be assigned as ground-return connections.
52.Avoid using resistor single inline packages (SIPs) unless there are separate return paths for each resistor.
53.Check the film to verify that antipads in via fields do not overlap and there is a well-defined web between clearance holes in the power and ground planes.
54.If a signal changes reference planes, the reference planes should be as closely spaced as you can afford. If you use a decoupling capacitor to minimize the impedance of the return path, its capacitance value is immaterial. Select it and design it in for lowest loop inductance.
55.If many signal lines switch reference planes, space the signal path vias as far apart as possible, rather than clustering them all in the same location.
56.If a signal switches reference layers, and the planes are the same voltage level, place a via between the return planes as close to the signal via as possible.
A.3 Minimize Rail Collapse
Strategy: Minimize the impedance of the power-distribution network.
Tactics:
57.Minimize the loop inductance between the power and ground paths.
58.Allocate power and ground planes on adjacent layers with as thin a dielectric as you can afford.
59.Get the lowest impedance between the planes by using as high a dielectric constant between the planes as you can afford.
60.Use as many power- and ground-plane pairs in parallel as you can afford.
61.Route the same currents far apart and opposite currents close together.
62.Place each power via as close as practical to a ground via. If you can't get them at least within a pitch equal to their length, there will be no coupling and no value in proximity.
63.Route the power and ground planes as close as possible to the surface where the decoupling capacitors are mounted.
64.Use multiple vias to the same power or ground pad, but keep the vias as far apart as possible.
65.Use vias as large in diameter as practical when routing to power or ground planes.
66.Use double-bonding on power and ground pads to minimize the loop inductance of the wire bonds.
67.Use as many power and ground connections from the chip as you can afford.
68.Use as many power and ground connections from the package as you can afford.
69.Use chip-interconnect methods that are as short as possible, such as flip-chip rather than wire-bond.
70.Use package leads as short as possible, such as chip-scale packages rather than QFP packages.
71.Keep all surface traces that run between the pads of the decoupling capacitors and their vias as short and wide as possible.
72.Use a total amount of bulk-decoupling capacitance to take over from the regulator at low frequency.
73.Use a total number of decoupling capacitors to reduce the equivalent inductance at high frequency.
74.Use as small a body size for a decoupling capacitor as you can afford and minimize the length of all connections from the capacitor pads to the power and ground planes.
75.Place as much decoupling capacitance as you can afford on the chip itself.
76.Place as many low-inductance decoupling capacitors as you can afford on the package.
77.Use differential pairs for I/Os.
A.4 Minimize EMI
Strategy: Reduce the voltage that drives common currents, increase the impedance of the common current paths, and shield and filter as a quick fix.
Tactics:
78.Reduce ground bounce.
79.Keep all traces at least five line widths from the edge of the board.
80.Route traces in stripline when possible.
81.Place the highest-speed/highest-current components as far from the I/O connections as possible.
82.Place the decoupling capacitors in proximity to the chips to minimize the spread of high-frequency-current components in the planes.
83.Keep power and ground planes on adjacent layers and as close together as possible.
84.Use as many power- and ground-plane pairs as you can afford.
85.When using multiple power- and ground-plane pairs, recess the power planes and then stitch shorting vias between the ground planes along the edges.
86.Use ground planes as surface layers, where possible.
87.Know the resonant frequency of all packages and change the package geometry if there is an overlap with a clock harmonic.
88.Avoid signals switching different voltage reference planes in a package. This will drive package resonances.
89.Add ferrite filter sheets to the top of packages if they might have a resonance.
90.Minimize any asymmetries between the lines in each differential pair
91.Use a common-signal-choke filter on all differential pair connections
92.Use a common-signal-choke filter around the outside of all peripheral cables.
93.Filter all external I/O lines to use the longest signal rise time that is tolerable for the timing budget.
94.Use spread-spectrum clock generator to spread the first harmonic over a wider frequency range and decrease the radiated energy within the bandwidth of the FCC test.
95.When connecting shielded cables, try to keep the shield as an extension of the enclosure.
96.Minimize the inductance of the shielded cable connections to the enclosure. Use a coaxial connection right from the end of the cable and to the enclosure.
97.Equipment bays should not penetrate the integrity of the enclosure.
98.Only interconnects need to break the enclosure integrity.
99.Keep aperture diameters small, significantly smaller than a wavelength of the lowest frequency radiation that might leak. More and smaller holes are better than fewer and larger holes.
100.The most expensive rule is the one that delays the product ship date.
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