This application report contains implementation instructions for the DDR2 interface contained on the TMS320C6472/TMS320TCI6486 DSP devices. The approach to specifying interface timing for the DDR2 interface is quite different than on previous devices.
The previous approach specified device timing in terms of data sheet specifications and simulation models. The customer was required to obtain compatible memory devices, as well as their data sheets and simulation models. The customer would then take this information and design their printed circuit
board (PCB) using high speed simulation to close system timing.
For the C6472/TCI6486 DDR2 interface, the approach is to specify compatible DDR2 devices and provide the PCB routing rule solution directly to the customer. TI has performed the simulation and system design work to ensure DDR2 interface timings are met. The DDR2 system solution is referred to as the C6472/TCI6486 DDR2 collateral. This document describes the content of this collateral. |
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