请帮帮我,这个程序有一个错误,请大侠帮我改改这个用MAX+plusII仿真谢谢!!library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity countrl is port( CLR: in std_logic; Fa: IN std_logic; Fb: in std_logic; Tp:in std_logic; Tt: buffer std_logic; phasen:out std_logic ); end; architecture behav of countrl is signal phas: std_logic; begin process(Tp,CLR,Fa) begin if CLR='1' then Tt<='0'; elsif Fa'event and Fa='1' then Tt<=Tp; end if; end process; process(fa,fb,clr) begin if clr='1' then phas<='0'; else phas<= fa xor fb ; end if; end process; phasen<=Tt and phas; end behav;
end if; end process; process(fa,fb,clr) begin if clr='1' then phas<='0'; else phas<= fa xor fb ; end if; end process; phasen<=Tt and phas; end behav;
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