library IEEE;
use IEEE.std_logic_1164.all;
entity Bcd2yu3 is
generic (data_width : natural := 8 );
port (cin : in std_logic(data_width downto 0);
cout : out std_logic(data_width downto 0););
end Bcd2yu3;
-- description of adder using concurrent signal assignments
architecture rtl of Bcd2yu3 is
begin
cout <= cin + "11";
end rtl;
|
楼主
标题置顶
标题高亮
