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library IEEE;<br />use IEEE.std_logic_1164.all;<br />entity Bcd2yu3 is <br /> generic (data_width : natural := 8 );<br /> port (cin : in std_logic(data_width downto 0);<br /> cout : out std_logic(data_width downto 0););<br />end Bcd2yu3;<br /><br /><br />-- description of adder using concurrent signal assignments<br />architecture rtl of Bcd2yu3 is<br />begin<br /> cout <= cin + "11";<br />end rtl;<br />
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