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fpga控制dds的问题

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强仔|  楼主 | 2007-11-15 21:44 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式
现在在调fpga控制dds的程序,wclk,8位data,freq_ud的时序都没问题,但就是出不来波形,请高手指点
程序如下
--0x40000000
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity dds_source is
    port(clk        :in std_logic;
         fpga_reset    :in std_logic;
         B_dir        :out std_logic_vector(7 downto 0);
         B_oe        :out std_logic_vector(7 downto 0);
         data        :out std_logic_vector(7 downto 0);
         wclk        :out std_logic;
         dds_reset    :out std_logic;
         freq_ud    :out std_logic
        );
end dds_source;

architecture behavior of dds_source is
signal clkdiv    :std_logic:='1';
begin
    B_dir    <= "00000000";
    B_oe    <= "00000000";
    
    process(clk)
    variable clkcnt    :std_logic_vector(7 downto 0);
    begin
        if clk'event and clk='1' then
            if clkcnt="00000001" then
                clkcnt    := (others=>'0');
                clkdiv    <= not clkdiv;
            else
                clkcnt    := clkcnt+1;
            end if;
        end if;
    end process;
    
    process(clkdiv)
    variable count    :integer range 0 to 15;
    variable cnt    :integer range 0 to 5;
    begin
        if fpga_reset='0' then
            wclk    <= '0';
            freq_ud    <= '0';
            count    := 0;
            cnt        := 0;
        elsif clkdiv'event and clkdiv='0' then
            case count    is
                when 0    =>
                        data        <= "00000000";
                        if cnt=2 then
                            wclk    <= '1';
                            cnt        := cnt+1;
                        elsif cnt=4 then
                            wclk    <= '0';
                            cnt        := cnt+1;
                        elsif cnt=5 then
                            count    := 1;
                            cnt        := 0;
                        else
                            cnt        := cnt+1;
                        end if;
                when 1     =>
                        data        <= "01000000";
                        if cnt=2 then
                            wclk    <= '1';
                            cnt        := cnt+1;
                        elsif cnt=4 then
                            wclk    <= '0';
                            cnt        := cnt+1;
                        elsif cnt=5 then
                            count    := 2;
                            cnt        := 0;
                        else
                            cnt        := cnt+1;
                        end if;
                when 2    =>
                        data        <= "00100000";
                        if cnt=2 then
                            wclk    <= '1';
                            cnt        := cnt+1;
                        elsif cnt=4 then
                            wclk    <= '0';
                            cnt        := cnt+1;
                        elsif cnt=5 then
                            count    := 3;
                            cnt        := 0;
                        else
                            cnt        := cnt+1;
                        end if;
                when 3    =>
                        data        <= "00010000";
                        if cnt=2 then
                            wclk    <= '1';
                            cnt        := cnt+1;
                        elsif cnt=4 then
                            wclk    <= '0';
                            cnt        := cnt+1;
                        elsif cnt=5 then
                            count    := 4;
                            cnt        := 0;
                        else
                            cnt        := cnt+1;
                        end if;

                when 4    =>
                        data        <= "00001000";
                        if cnt=2 then
                            wclk    <= '1';
                            cnt        := cnt+1;
                        elsif cnt=4 then
                            wclk    <= '0';
                            cnt        := cnt+1;
                        elsif cnt=5 then
                            count    := 5;
                            cnt        := 0;
                        else
                            cnt        := cnt+1;
                        end if;
                when 5    =>
                        data        <="00000000";
                        if cnt=5 then
                            count    := 6;
                            cnt        := 0;
                            freq_ud    <= '0';
                        else
                            cnt        := cnt+1;
                            freq_ud    <= '1';
                        end if;
                when 6    =>
                        dds_reset    <= '1';
                        if cnt=5 then
                            count    := 0;
                            cnt        := 0;
                        else
                            cnt        := cnt+1;
                        end if;
                when others    =>
                        count    :=0;
            end case;
        end if;
    end process;
end behavior;

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