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小弟写的状态机,欢迎大神点评

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本帖最后由 damoyeren 于 2013-8-7 17:36 编辑


用case when 语句写的
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity machine is
port (clk,nw,rst:in std_logic;
   sel:out std_logic_vector(1 downto 0);
   first,nxt:out std_logic);
end machine;
architecture behave of machine is
  type state_machine is (idle,s1,s2,s3,s4);
  signal current_state,next_state:state_machine;
  signal filter:state_machine:=current_state;
begin
process (clk,rst)
begin
if clk'event and clk='1' then
     if rst='0' then
   current_state<=idle;
  else
   current_state<=next_state;
   case next_state is
    when  idle=>if nw='1' then
       filter<=s1;
       end if;
    when  s1=>filter<=s2;
    when  s2=>filter<=s3;
    when  s3=>filter<=s4;
    when  s4=>if nw='1' then
        filter<=s1;
        else
        filter<=idle;
        end if;
   end case;
  end if;
end if;
end process;

process(filter)
begin
case filter is
when idle=>first<='0';nxt<='0';
when s1=>sel<="00";first<='1';
when s2=>sel<="01";first<='0';
when s3=>sel<="10";
when s4=>sel<="11";nxt<='1';
end case;
end process;
end behave;

用if then elsif 语句


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity machine1 is
port (clk,nw,rst:in std_logic;
   sel:out std_logic_vector(1 downto 0);
   first,nxt:out std_logic);
end machine1;
architecture behave of machine1 is
  type state_machine is (idle,s1,s2,s3,s4);
  signal current_state,next_state:state_machine;
  signal filter:state_machine:=current_state;
begin
process (clk,rst)
begin
if clk'event and clk='1' then
     if rst='0' then
   current_state<=idle;
  else
   current_state<=next_state;
   case next_state is
    when  idle=>if nw='1' then
       filter<=s1;
       end if;
    when  s1=>filter<=s2;
    when  s2=>filter<=s3;
    when  s3=>filter<=s4;
    when  s4=>if nw='1' then
        filter<=s1;
        else
        filter<=idle;
        end if;
   end case;
  end if;
end if;
end process;

process(filter)
begin
if current_state=idle then
first<='0';nxt<='0';
elsif current_state=s1 then
sel<="00";first<='1';
elsif current_state=s2 then
sel<="01";first<='0';
elsif current_state=s3 then
sel<="10";
elsif current_state=s4 then
sel<="11";nxt<='1';
end if;
end process;
end behave;


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