entity top is
Port ( btn_0 : in STD_LOGIC;
clk : in STD_LOGIC;
led : out STD_LOGIC);
end top;
architecture Behavioral of top is
constant CNTR_MAX : std_logic_vector(15 downto 0) := (others => '1');
signal btn0_cntr : std_logic_vector(15 downto 0) := (others => '0');
signal led_r : std_logic := '0';
signal btn0_reg : std_logic := '0';
begin
btn0_debounce_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (btn0_cntr = CNTR_MAX) then
btn0_reg <= not(btn0_reg);
end if;
end if;
end process;
btn0_counter_process : process (CLK)
begin
if (rising_edge(CLK)) then
if ((btn0_reg = '1') xor (btn_0 = '1')) then
if (btn0_cntr = CNTR_MAX) then
btn0_cntr <= (others => '0');
else
btn0_cntr <= btn0_cntr + 1;
end if;
else
btn0_cntr <= (others => '0');
end if;
end if;
end process;
process(btn0_reg)
begin
if rising_edge(btn0_reg) then
led_r <= not (led_r);
end if;
end process;
led <= led_r;
end Behavioral;
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