语法没错误，但都是警告。。。下载到FPGA，LCD只有亮光，没有显示数据。。。程序如下：library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity lcd1602 is
port
(
clk :in std_logic;
rst :in std_logic;
LCD_D : out std_logic_vector(7 downto 0);
LCD_E : out std_logic;
LCD_RS : out std_logic;
LCD_RW : out std_logic
);
end ;
architecture fun of lcd1602 is
signal reset : std_logic;
signal clk_e : std_logic:='0';
signal cnt_e : integer range 0 to 500000 ;
signal cnt_delay : integer range 0 to 9 ;
signal lcd_status : integer ;
constant lcd_idle : integer:=0; --开机等待
constant lcd_clear: integer:=1; --清屏
constant lcd_set : integer:=2; --功能设置
constant lcd_swit : integer:=3; --显示开关设置
constant lcd_mod : integer:=4; --输入方式设置
constant lcd_init : integer:=5; --初始化完成等待1.64ms
constant lcd_wrreg: integer:=6; --写寄存器
---=====初始化====----
--清屏
constant clear : std_logic_vector(7 downto 0):="00000001";
--功能设置
constant f_set : std_logic_vector(2 downto 0):="001" ;
constant DL : std_logic:='1' ; --接口数据位设置
constant N : std_logic:='1' ; --行数设置
constant F : std_logic_vector:="0" ; --字形设置
--显示开关控制
constant swit : std_logic_vector(4 downto 0):="00001";
constant D : std_logic:='1'; --调整显示开关
constant C : std_logic:='0'; --光标开关
constant B : std_logic:='0'; --字符闪烁开关
--输入方式设置
constant modset : std_logic_vector(5 downto 0):="000001";
constant ID : std_logic:='1'; --光标移动方式
constant S : std_logic:='0'; --整体显示位移
---===写寄存器===---
signal com_data : std_logic_vector(7 downto 0):=(others=>'0') ;--指令
signal data : std_logic_vector(7 downto 0):=(others=>'0') ;--数据
signal wr_reg : std_logic_vector(1 downto 0) :=(others=>'0'); --写寄存器标志 01： 写指令 10：写数据
----==========-----
signal sig_en : std_logic:='0' ; --写数据计数器使能
signal sys_cnt : integer range 0 to 33 ; -- 写数据计数器
signal sig_end,sig_end_d : std_logic:='0' ; --写数据结束标志
begin
reset<= not rst;
--reset<= rst;
LCD_E<= clk_e;
process(clk,reset) --- 时钟分频
begin
if reset='1' then
cnt_e<=0;
clk_e<='0' ;
elsif falling_edge(clk) then
if sig_end_d='0' then
if cnt_e=500000 then
cnt_e<=0;
clk_e<=not clk_e;
else
cnt_e<=cnt_e+1;
end if ;
else
clk_e<='1';
end if ;
end if ;
end process;
-----status
process(clk_e,reset)
begin
if reset='1' then
lcd_status<=lcd_idle;
elsif falling_edge(clk_e) then
case lcd_status is
when lcd_idle =>cnt_delay<=cnt_delay+1 ;--开机等待
if cnt_delay= 9 then
lcd_status<=lcd_clear;
end if ;
when lcd_clear =>lcd_status<=lcd_set;--清屏01
when lcd_set =>lcd_status<=lcd_swit;--功能设置3C
when lcd_swit =>lcd_status<=lcd_mod;--显示状态开关设置0C
when lcd_mod =>lcd_status<=lcd_init;--输入方式设置06
when lcd_init =>if wr_reg="01" or wr_reg="10" then --初始化完成等待1.64ms
lcd_status<=lcd_wrreg;
end if ;
when lcd_wrreg => if wr_reg="00" then --写数据
lcd_status<=lcd_init;
end if ;
when others=>lcd_status<=lcd_idle;
end case;
end if ;
end process;
-----status data
process(clk_e,reset)
begin
if reset='1' then
LCD_RS <='0';
LCD_RW <='0';
LCD_D <=(others=>'0');
elsif falling_edge(clk_e) then
if lcd_status=lcd_clear then
LCD_RS <='0';
LCD_RW <='0';
LCD_D <=clear;
elsif lcd_status=lcd_set then
LCD_RS <='0';
LCD_RW <='0';
LCD_D <= f_set & DL & N & F & "00" ;
elsif lcd_status=lcd_swit then
LCD_RS <='0';
LCD_RW <='0';
LCD_D <=swit & D & C & B;
elsif lcd_status=lcd_mod then
LCD_RS <='0';
LCD_RW <='0';
LCD_D <= modset & ID & S;
elsif lcd_status=lcd_wrreg then ---- 寄存器写
if wr_reg="01" then
LCD_RS <='0';
LCD_RW <='0';
LCD_D <=com_data ;
elsif wr_reg="10" then
LCD_RS <='1';
LCD_RW <='0';
LCD_D <=data ;
end if ;
else
LCD_RS <='0';
LCD_RW <='0';
LCD_D <=(others=>'0');
end if ;
end if ;
end process;
--- 输入显示内容
process(lcd_status,sig_end)
begin
if lcd_status=lcd_wrreg then
sig_en<='1' ;
elsif sig_end='1' then
sig_en<='0' ;
else
sig_en<='0';
end if ;
end process;
process(clk_e,reset)
begin
if reset='1' then
sys_cnt<=0;
elsif falling_edge(clk_e) then
if sig_en='1' then
if sys_cnt=33 then
sys_cnt<=0;
else
sys_cnt<=sys_cnt + 1 ;
end if ;
else
sys_cnt<=0;
end if ;
end if ;
end process;
process(clk_e,reset)
begin
if reset='1' then
sig_end_d<='0';
elsif falling_edge(clk_e) then
sig_end_d<=sig_end ;
end if ;
end process;
process(sys_cnt)
begin
case sys_cnt is
when 0 => data<=x"48"; --H
wr_reg<="10";
sig_end<='0';
when 1 => data<=x"65"; --e
wr_reg<="10";
sig_end<='0';
when 2 => data<=x"6c"; --l
wr_reg<="10";
sig_end<='0';
when 3 => data<=x"6c"; --l
wr_reg<="10";
sig_end<='0';
when 4 => data<=x"6f"; --o
wr_reg<="10";
sig_end<='0';
when 5 => data<=x"21"; --!
wr_reg<="10";
sig_end<='0';
when 6 => data<=x"21"; --!
wr_reg<="10";
sig_end<='0';
when 7 => data<=x"A0"; --space
wr_reg<="10";
sig_end<='0';
when 8 => data<=x"7E"; -- ->
wr_reg<="10";
sig_end<='0';
when 9 => data<=x"A0"; --space
wr_reg<="10";
sig_end<='0';
when 10 => data<=x"5A";--Z
wr_reg<="10";
sig_end<='0';
when 11 => data<=x"52"; --R
wr_reg<="10";
sig_end<='0';
when 12 => data<=x"74"; --t
wr_reg<="10";
sig_end<='0';
when 13 => data<=x"65"; --e
wr_reg<="10";
sig_end<='0';
when 14 => data<=x"63"; --c
wr_reg<="10";
sig_end<='0';
when 15 => data<=x"68"; --h
wr_reg<="10";
sig_end<='0';
when 16 => com_data<=x"C0"; -- 换行
wr_reg<="01";
sig_end<='0';
when 17 => data<=x"77"; --w
wr_reg<="10";
sig_end<='0';
when 18 => data<=x"77"; --w
wr_reg<="10";
sig_end<='0';
when 19 => data<=x"77"; --w
wr_reg<="10";
sig_end<='0';
when 20 => data<=x"2E"; --.
wr_reg<="10";
sig_end<='0';
when 21 => data<=x"5A"; --Z
wr_reg<="10";
sig_end<='0';
when 22 => data<=x"52"; --R
wr_reg<="10";
sig_end<='0';
when 23 => data<=x"B0"; -- -
wr_reg<="10";
sig_end<='0';
when 24 => data<=x"74"; --t
wr_reg<="10";
sig_end<='0';
when 25 => data<=x"65"; --e
wr_reg<="10";
sig_end<='0';
when 26 => data<=x"63"; --c
wr_reg<="10";
sig_end<='0';
when 27 => data<=x"68"; --h
wr_reg<="10";
sig_end<='0';
when 28 => data<=x"2E"; --.
wr_reg<="10";
sig_end<='0';
when 29 => data<=x"6E"; --n
wr_reg<="10";
sig_end<='0';
when 30 => data<=x"65"; --e
wr_reg<="10";
sig_end<='0';
when 31 => data<=x"74"; --t
wr_reg<="10";
sig_end<='0';
when 32 => data<=x"A0"; --space
wr_reg<="10";
sig_end<='0';
when 33 => wr_reg<="00";
sig_end<='1';
when others=>wr_reg<="00";
sig_end<='1';
end case;
end process;
end ;
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