自定义ram问题

只看该作者 · 2013-10-4 15:59

本帖最后由 sen19890606 于 2013-10-4 17:05 编辑

新手写了一个FPGA接受ARM指令的程序，将三个20位的指令分为15个时钟依次写进FPGA（每次写4位），原理是先写入ram缓存，写完后再读进FPGA。
但是为什么寄存器组没有综合成ram呢，这样消耗好多寄存器资源。如果我把寄存器组定义为reg [3:0] wbuffer [0:31]，即将寄存器组扩大后，就可以综合为ram，但读写又会出现问题，出现如下警告
Warning: Inferred dual-clock RAM node "d2fpga:d2fpga|buffer_rtl_0" from synchronous design logic.  The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design.
请大神指点
module d2fpga(en,wclk,clk,data,control,over,ST,ED,FS);
//control高电平有效，写buffer使能，需一直保持高电平，否则wpt会被清零，影响之后的参数读取；
//over在参数存储完毕后，保持高电平直至en清零
//data由wclk控制写入，在control高电平期间每个上升沿写一组
input en,clk,wclk,control;
input [3:0] data;
output reg over;
output reg [19:0] ST,ED,FS;
reg [3:0] wbuffer [0:15];
///////////////////////////////////////////
reg [3:0] wpt;
always@(posedge wclk or negedge control)
begin
if(!control)
wpt<=4'd0;
   else
   begin
      wbuffer[wpt]<=data;
   wpt<=wpt+4'd1;
   end
end
////////////////////////////////////////
reg ready1,ready;
wire ready2;
assign ready2=(wpt==4'd15)?1'b1:1'b0;
always@(posedge clk or negedge en)
begin
if(!en)
   begin
      ready1<=1'b0;
   ready<=1'b0;
   end
   else
   begin
      ready1<=ready2;
   ready<=ready1;
   end
end
///////////////////////////////////////
reg [3:0] rpt;
always@(posedge clk or negedge en)
begin
if(!en)
   begin
      rpt<=4'd0;
      ST<=20'd0;
   ED<=20'd0;
   FS<=20'd0;
   over<=1'b0;
   end
   else
   begin
      if(ready)
   begin
      case(rpt)
         0: begin ST[3:0]<=wbuffer[rpt];rpt<=rpt+4'd1;over<=1'b0; end
         1: begin ST[7:4]<=wbuffer[rpt];rpt<=rpt+4'd1;over<=1'b0; end
         2: begin ST[11:8]<=wbuffer[rpt];rpt<=rpt+4'd1;over<=1'b0; end
         3: begin ST[15:12]<=wbuffer[rpt];rpt<=rpt+4'd1;over<=1'b0; end
4: begin ST[19:16]<=wbuffer[rpt];rpt<=rpt+4'd1;over<=1'b0; end
         5: begin ED[3:0]<=wbuffer[rpt];rpt<=rpt+4'd1;over<=1'b0; end
         6: begin ED[7:4]<=wbuffer[rpt];rpt<=rpt+4'd1;over<=1'b0; end
         7: begin ED[11:8]<=wbuffer[rpt];rpt<=rpt+4'd1;over<=1'b0; end
         8: begin ED[15:12]<=wbuffer[rpt];rpt<=rpt+4'd1;over<=1'b0; end
9: begin ED[19:16]<=wbuffer[rpt];rpt<=rpt+4'd1;over<=1'b0; end
         10: begin FS[3:0]<=wbuffer[rpt];rpt<=rpt+4'd1;over<=1'b0; end
         11: begin FS[7:4]<=wbuffer[rpt];rpt<=rpt+4'd1;over<=1'b0; end
         12: begin FS[11:8]<=wbuffer[rpt];rpt<=rpt+4'd1;over<=1'b0; end
         13: begin FS[15:12]<=wbuffer[rpt];rpt<=rpt+4'd1;over<=1'b0; end
14: begin FS[19:16]<=wbuffer[rpt];rpt<=rpt+4'd1;over<=1'b0; end
default: begin ST<=ST;ED<=ED;FS<=FS;rpt<=rpt;over<=1'b1; end
endcase
   end
   else
   begin
      ST<=ST;
ED<=ED;
FS<=FS;
over<=over;
rpt<=rpt;
   end
   end
end
endmodule