GD32F105/107的时钟配置 108M

只看该作者 · 2013-10-30 17:31

105，107的RCC寄存器中，RCC_CFGR的PLLMUL[4]由Bit27换到了bit29，因为bit27被MCO[3]占了，所以108M的配置有点小的变化。
另外105，107的HSE一般接的25M晶振，所以配置过程如下：

static void SetSysClockTo108(void)
{
  __IO uint32_t StartUpCounter = 0,HSEStatus = 0;
  __IO uint16_t GigadeviceID = 0;

  /*ID check*/
  if( *( uint8_t *)( 0xE00FFFE8 ) & 0x08 )
  {
   GigadeviceID = ( ( *( uint8_t *)( 0xE00FFFD0 ) & 0x0F ) << 8 ) |
               ( ( *( uint8_t *)( 0xE00FFFE4 ) & 0xFF ) >> 3  )  |
               ( ( *( uint8_t *)( 0xE00FFFE8 ) & 0x07 ) << 5 ) + 1 ;
  }
  if(GigadeviceID != 0x7A3)return;

  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
  /* Enable HSE */
  RCC->CR |= ((uint32_t)RCC_CR_HSEON);

  /* Wait till HSE is ready and if Time out is reached exit */
  do
  {
HSEStatus = RCC->CR & RCC_CR_HSERDY;
StartUpCounter++;
  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));

  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
  {
/* HCLK = SYSCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
/* PCLK1 = HCLK/2 */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;

#ifdef STM32F10X_CL
/* Configure PLLs ------------------------------------------------------*/
/* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */

RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
                           RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
                           RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);

/* Enable PLL2 */
RCC->CR |= RCC_CR_PLL2ON;
/* Wait till PLL2 is ready */
while((RCC->CR & RCC_CR_PLL2RDY) == 0)
{
}

/* PLL configuration: PLLCLK = PREDIV1 * 27 = 108 MHz */
RCC->CFGR &= (uint32_t)~( RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
RCC->CFGR |= (uint32_t)(0x20000000 | RCC_CFGR_PLLSRC_PREDIV1 |
                        RCC_CFGR_PLLMULL12);
#else
/*  PLL configuration: PLLCLK = HSE/2* (15+12) = 108 MHz */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
                                    RCC_CFGR_PLLMULL));
RCC->CFGR |= (uint32_t)(0x08000000 | RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL12);

#endif

/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;
while((RCC->CR & RCC_CR_PLLRDY) == 0){}

/* Select PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08){}

  }
  else
  { /* If HSE fails to start-up, the application will have wrong clock
      configuration. User can add here some code to deal with this error */
  }
}