| ococ 发表于 2014-5-19 18:47  贴个你modelsim仿真的图
LIBRARY ieee;
 USE ieee.std_logic_1164.all;
 USE ieee.std_logic_unsigned.all;
 entity addr_a is
 port( clk,load:in std_logic;
 m:in std_logic_vector(7 downto 0);
 addr:buffer std_logic_vector(23 downto 0)
 
 );
 end;
 
 ARCHITECTURE  one of addr_a is
 
 
 signal dlta:std_logic_vector(23 downto 0);
 signal sum:std_logic_vector(23 downto 0):=(others=>'0');
 
 begin
 process(load,m)
 begin
 if load'event and load='1' then
 dlta(7 downto 0)<=m;
 end if;
 dlta(23 downto 8) <=(others=>'0');
 end process;
 
 sum <= dlta + sum;
 
 process(clk,sum)
 begin
 if clk'event and clk='1' then
 addr<=sum;
 end if;
 end process;
 
 end one;
 
 
 
 
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