`timescale 100 ns/1 ps
module SPI_Main_tb(SCK,CS,MOSI,MISO);
parameter CODE_R=8'h0A; //SPI读命令
parameter CODE_W=8'h05; //SPI写命令
parameter SCK_DELAY=100;
input MOSI;
output SCK,CS,MISO;
reg reg_SCK;
reg reg_CS;
wire MOSI;
reg reg_MISO;
reg [7:0] reg_readdat;
integer int_rdat,int_wdat;
assign MISO=reg_MISO;
assign SCK=reg_SCK;
assign CS=reg_CS;
always #(SCK_DELAY) reg_SCK = ~reg_SCK;
initial
begin
reg_SCK=0;
reg_CS=1;
reg_MISO=1;
reg_readdat=0;
int_rdat=0;
int_wdat=0;
#(SCK_DELAY*50);
read_dat();
read_dat1();
read_dat();
write_dat1();
read_dat();
write_dat();
read_dat();
end
task write_dat;
begin
senddat(CODE_W);
senddat(0);
senddat(1);
senddat(2);
senddat(3);
senddat(4);
senddat(5);
senddat(6);
@(negedge reg_SCK);
reg_CS=1;
#(SCK_DELAY*10);
end
endtask
task read_dat;
begin
senddat((CODE_R));
senddat(0);
@(posedge reg_SCK);
readdat();
readdat();
readdat();
readdat();
readdat();
readdat();
@(posedge reg_SCK);
reg_CS=1;
#(SCK_DELAY*10);
end
endtask
task write_dat1;
begin
senddat((CODE_W+1));
senddat(0);
senddat(1);
senddat(2);
senddat(3);
senddat(4);
senddat(5);
senddat(6);
@(negedge reg_SCK);
reg_CS=1;
#(SCK_DELAY*10);
end
endtask
task read_dat1;
begin
senddat(CODE_R+1);
senddat(0);
@(posedge reg_SCK);
readdat();
readdat();
readdat();
readdat();
readdat();
readdat();
@(posedge reg_SCK);
reg_CS=1;
#(SCK_DELAY*10);
end
endtask
task senddat;
input[7:0] sdat;
integer i;
begin
int_wdat=sdat;
for(i=0;i<8;i=i+1)
begin
@(negedge reg_SCK) reg_MISO=sdat[7];
reg_CS=0;
sdat=sdat<<1;
end
end
endtask
task readdat;
integer i;
begin
for(i=0;i<8;i=i+1)
begin
@(posedge reg_SCK) reg_readdat={reg_readdat[6:0],MOSI};
reg_CS=0;
end
int_rdat=reg_readdat;
end
endtask
endmodule
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