本帖最后由 dong_abc 于 2014-5-25 01:49 编辑
我做过这个功能。 PTC4和 llwu 都设置成输入中断。PTC4下降沿唤醒单片机,同时进入llwu中断。
void Config_pushbutton(void)
{
FGPIOC_PDDR &= ~(0x10); // Configure as input
PORTC_PCR4 = (PORT_PCR_MUX(1)
| PORT_PCR_PE_MASK
| PORT_PCR_PS_MASK
| PORT_PCR_IRQC(0xA));
/* Set the ICPR and ISER registers accordingly */
NVIC_ICPR |= (uint32)(1 << ((INT_PORTC_PORTD-16)%32));
NVIC_ISER |= (uint32)(1 << ((INT_PORTC_PORTD-16)%32));
set_irq_priority(INT_PORTC_PORTD-16, 3);
}
PE_ISR(Pushbutton_Interrupt)
{
if(MCM_CPO & MCM_CPO_CPOACK_MASK){
MCM_CPO &= ~MCM_CPO_CPOREQ_MASK;
while (MCM_CPO & MCM_CPO_CPOACK_MASK);
}
if ((PORTC_PCR4 & PORT_PCR_ISF_MASK) == PORT_PCR_ISF_MASK)
{
PORTC_PCR4 |= PORT_PCR_ISF_MASK;
}
}
void low_power_init(void)
{
/*PTC4is configured to wake up MCU from VLLSx and LLS modes, Interrup is ne*/
enable_irq(INT_LLW-16);
set_irq_priority(INT_LLW-16, 1);
llwu_configure(0x0100/*PTC4*/, LLWU_PIN_FALLING, 0x1);
PORTC_PCR4 = PORT_PCR_PS_MASK |
PORT_PCR_PE_MASK |
PORT_PCR_PFE_MASK |
PORT_PCR_IRQC(10) | /* IRQ Falling edge */
PORT_PCR_MUX(1);
enable_irq(31); //Enable GPIO interrupts on PORTC
}
PE_ISR(llw_isr){
if (LLWU_F2 & LLWU_F2_WUF8_MASK) {
LLWU_F2 |= LLWU_F2_WUF8_MASK; // write one to clear the flag
if(mpu_time_mode) {mpu_25ms_cnt++;}
else mpu_25ms_cnt = 0;
if(sedent_monit_mode) sedent_time_cnt++;
else sedent_time_cnt=0;
}
//***********************************************************************
// * Note: This ISR does not write to the LLWU_F3 register because these
// * are peripheral module wakeups. The flags contained in the LLWU_F3
// * register should be cleared through the associated module interrupt
// * and not through the LLWU_F3 per the Kinetis L Family Reference
// * Manual (LLWU Chapter)
// *********************************************************************
if (LLWU_F3 & LLWU_F3_MWUF0_MASK) {
SIM_SCGC5 |= SIM_SCGC5_LPTMR_MASK;
LPTMR0_CSR |= LPTMR_CSR_TCF_MASK; // write 1 to TCF to clear the LPT timer compare flag
LPTMR0_CSR = ( LPTMR_CSR_TEN_MASK | LPTMR_CSR_TIE_MASK | LPTMR_CSR_TCF_MASK );
}
if(LLWU_FILT1 & LLWU_FILT1_FILTF_MASK){
LLWU_FILT1 |= LLWU_FILT1_FILTF_MASK;
}
if(LLWU_FILT2 & LLWU_FILT2_FILTF_MASK){
LLWU_FILT2 |= LLWU_FILT2_FILTF_MASK;
}
NVIC_ICPR |= 1 << (LLWU_irq_no%32);
}
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