// On TMX samples, to get the best performance of on chip RAM blocks M0/M1/L0/L1/H0 internal
// control registers bit have to be enabled. The bits are in Device emulation registers.
DevEmuRegs.M0RAMDFT = 0x0300;
DevEmuRegs.M1RAMDFT = 0x0300;
DevEmuRegs.L0RAMDFT = 0x0300;
DevEmuRegs.L1RAMDFT = 0x0300;
DevEmuRegs.H0RAMDFT = 0x0300;
// Initalize PLL
SysCtrlRegs.PLLCR = 0xA;
// Wait for PLL to lock
for(i= 0; i< 5000; i++){}
// HISPCP/LOSPCP prescale register settings, normally it will be set to default values
SysCtrlRegs.HISPCP.all = 0x0001;
SysCtrlRegs.LOSPCP.all = 0x0002;
// Peripheral clock enables set for the selected peripherals.
SysCtrlRegs.PCLKCR.bit.EVAENCLK=1;
SysCtrlRegs.PCLKCR.bit.EVBENCLK=1;
// SysCtrlRegs.PCLKCR.bit.SCIENCLKA=1;
// SysCtrlRegs.PCLKCR.bit.SCIENCLKB=1;
SysCtrlRegs.PCLKCR.bit.ADCENCLK=1;
// On TMX samples, to get the best performance of on chip RAM blocks M0/M1/L0/L1/H0 internal
// control registers bit have to be enabled. The bits are in Device emulation registers.
DevEmuRegs.M0RAMDFT = 0x0300;
DevEmuRegs.M1RAMDFT = 0x0300;
DevEmuRegs.L0RAMDFT = 0x0300;
DevEmuRegs.L1RAMDFT = 0x0300;
DevEmuRegs.H0RAMDFT = 0x0300;
// Initalize PLL
SysCtrlRegs.PLLCR = 0xA;
// Wait for PLL to lock
for(i= 0; i< 5000; i++){}
// HISPCP/LOSPCP prescale register settings, normally it will be set to default values
SysCtrlRegs.HISPCP.all = 0x0001;
SysCtrlRegs.LOSPCP.all = 0x0002;
// Peripheral clock enables set for the selected peripherals.
SysCtrlRegs.PCLKCR.bit.EVAENCLK=1;
SysCtrlRegs.PCLKCR.bit.EVBENCLK=1;
// SysCtrlRegs.PCLKCR.bit.SCIENCLKA=1;
// SysCtrlRegs.PCLKCR.bit.SCIENCLKB=1;
SysCtrlRegs.PCLKCR.bit.ADCENCLK=1;