本帖最后由 xmar 于 2014-5-31 11:38 编辑
这个更方便：
module seriData(clk, data_out);
input clk;
output data_out;
reg data_out;
reg [3:0] count;
reg [15:0] workr;
paramter N = 16'hB3A1;
always @(posedge clk)
begin
workr <= (16’h8000 >> count);
count <= count + 1;
if(workr & N)
data_out <= 1;
else
data_out <= 0;
end
endmodule
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