#ifdef USB_OTG_HS_CORE
#define RX_FIFO_HS_SIZE 512
#define TX0_FIFO_HS_SIZE 128
#define TX1_FIFO_HS_SIZE 384
#define TX2_FIFO_HS_SIZE0
#define TX3_FIFO_HS_SIZE0
#define TX4_FIFO_HS_SIZE0
#define TX5_FIFO_HS_SIZE0
#endif
在上面的代码中,有两个问题:
(1)为什么发送缓冲区都分TX1和TX2,而接收不用分,就是一个整的??
(2)接收和发送的FIFO的大小设置的依据在哪里呢?? |