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TB代码
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY gg IS
END gg;
ARCHITECTURE behavior OF gg IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Active_video_detect20140922
PORT(
RstN_in : IN std_logic;
VCLK_in : IN std_logic;
Video_in : IN std_logic_vector(19 downto 0);
Video_out : OUT std_logic_vector(19 downto 0)
);
END COMPONENT;
--Inputs
signal RstN_in : std_logic := '0';
signal VCLK_in : std_logic := '0';
signal Video_in : std_logic_vector(19 downto 0) := (others => '0');
--Outputs
signal Video_out : std_logic_vector(19 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant VCLK_in_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Active_video_detect20140922 PORT MAP (
RstN_in => RstN_in,
VCLK_in => VCLK_in,
Video_in => Video_in,
Video_out => Video_out
);
-- Clock process definitions
VCLK_in_process :process
begin
VCLK_in <= '0';
wait for VCLK_in_period/2;
VCLK_in <= '1';
wait for VCLK_in_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
RstN_in <= '0';
wait for 100 ns;
RstN_in <= '1';
-- wait for <clock>_period*10;
-- insert stimulus here
wait;
end process;
process(RstN_in,VCLK_in)
begin
if RstN_in = '0' then
Video_in <= (others => '0');
elsif VCLK_in'event and VCLK_in = '1' then
Video_in <= Video_in + '1';
end if;
end process;
END;
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