nethopper 发表于 2014-10-31 00:29 
如果下载程序后，从设备管理器中看，电脑能自动找到与下载的程序中设置的PID和VID匹配的驱动程序，但Consol ...
谢谢。MISC页上有显示这个sys。
再请教一个问题，就是我用的是56Pin的，如图所示（图再加个PF输出到FPGA），我没有连CY的中断引脚（PA1，PA0），功能是FPGA采集到的数据传给上位机。。。。那么我没加中断信号的话，上位机怎么告诉我我可以发送数据了，这是我修改的固件，我还需要加点什么？
void TD_Init( void )
{
CPUCS = 0x12; // CLKSPD[1:0]=10, for 48MHz operation, output CLKOUT
PINFLAGSAB = 0x6E; // FLAGA - EP6PF ,FALGB-EP6FF
SYNCDELAY;
PINFLAGSCD = 0x00;
SYNCDELAY;
PORTACFG |= 0x40; //FLAGD-SLCS
SYNCDELAY;
IFCONFIG = 0xE3; //Internal clock, 48 MHz, Slave FIFO interface
SYNCDELAY;
// IFCLKSRC=1 , FIFOs executes on internal clk source
// xMHz=1 , 48MHz operation
// IFCLKOE=1 ,Drive IFCLK pin signal at 48MHz
// IFCLKPOL=0 , Don't invert IFCLK pin signal from internal clk
// ASYNC=0 , master samples synchronous
// GSTATE=0 , Don't drive GPIF states out on PORTE[2:0], debug WF
// IFCFG[1:0]=11, FX2 in slave FIFO mode
// Registers which require a synchronization delay, see section 15.14
// FIFORESET FIFOPINPOLAR
// INPKTEND OUTPKTEND
// EPxBCH:L REVCTL
// GPIFTCB3 GPIFTCB2
// GPIFTCB1 GPIFTCB0
// EPxFIFOPFH:L EPxAUTOINLENH:L
// EPxFIFOCFG EPxGPIF标志寄存器SEL
// PINFLAGSxx EPxFIFOIRQ
// EPxFIFOIE GPIFIRQ
// GPIFIE GPIFADRH:L
// UDMACRCH:L EPxGPIFTRIG
// GPIFTRIG
// Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
// ...these have been replaced by GPIFTC[B3:B0] registers
// EP4 and EP8 are not used in this implementation...
EP2CFG = 0x01; //clear valid bit
SYNCDELAY;
EP6CFG = 0xE0; // in 512 bytes, 4x, bulk
SYNCDELAY;
EP4CFG = 0x02; //clear valid bit
SYNCDELAY;
EP8CFG = 0x02; //clear valid bit
SYNCDELAY;
SYNCDELAY;
FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions
SYNCDELAY; // see TRM section 15.14
FIFORESET = 0x02; // reset, FIFO 2
SYNCDELAY; //
FIFORESET = 0x04; // reset, FIFO 4
SYNCDELAY; //
FIFORESET = 0x06; // reset, FIFO 6
SYNCDELAY; //
FIFORESET = 0x08; // reset, FIFO 8
SYNCDELAY; //
FIFORESET = 0x00; // deactivate NAK-ALL
// handle the case where we were already in AUTO mode...
// ...for example: back to back firmware downloads...
SYNCDELAY; //
EP6FIFOCFG = 0x0D; // AUTOIN=1, ZEROLENIN=1, WORDWIDE=1
SYNCDELAY;
//JTAG Enable and SYNC signals for ZTEX Spartan 6 module 1.1 (FGPA+FX2LP setup)
OEB&=0x00;
OED&=0x00;
}
void TD_Poll( void )
{ // Called repeatedly while the device is idle
}
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