本人使用天嵌E9的 DEMO, 使用《I.MX6DQSDL DDR3 Script Aid V0.10》脚本生成RealView.inc，
本人的脚本配置
Device Information
Manufacturer: Samsung
Memory part number: K4B4G1646B HCK0
Memory type: DDR3-1600 1600
DRAM density (Gb) 4
DRAM Bus Width 16
Number of Banks 8
Number of ROW Addresses 15
Number of COLUMN Addresses 10
Page Size (K) 2
Self-Refresh Temperature (SRT) Normal
tRCD=tRP=CL (ns) 20.834
tRC Min (ns) 73.866
tRAS Min (ns) 53.032
System Information
i.Mx Part i.Mx6Q Arik
Bus Width 64
Density per chip select (Gb) 16
Number of Chip Selects used 1 If only one CS is used, that must be CS0.
Total DRAM Density (Gb) 16
DRAM Clock Freq (MHz) 528
DRAM Clock Cycle Time (ns) 1.894
Address Mirror (for CS1) Disable
SI Configuration
DRAM DSE Setting - DQ/DQM (ohm) 40 40ohm is used in FSL reference design.
DRAM DSE Setting - ADDR/CMD/CTL (ohm) 40 40ohm is used in FSL reference design.
DRAM DSE Setting - CK (ohm) 40 40ohm is used in FSL reference design.
DRAM DSE Setting - DQS (ohm) 40 40ohm is used in FSL reference design.
System ODT Setting (ohm) 40
生成的表转化成 u-boot 里面的格式，
dcd_hdr: .word 0x40A802D2 /* Tag=0xD2, Len=84*8 + 4 + 4 = , Ver=0x40 */
write_dcd_cmd: .word 0x04A402CC /* Tag=0xCC, Len=84*8 + 4 = , Param=0x04 */
//,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
//init script for i.Mx6Q DDR3 E9
//,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
// Revision History
// v01
//,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
// IOMUX
//,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
// IOMUXC_BASE_ADDR = 0x020e 0000
//DDR IO TYPE:
MXC_DCD_ITEM(1,0x020e0798 , 0x000C0000) // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
MXC_DCD_ITEM(2,0x020e0758 , 0x00000000) // IOMUXC_SW_PAD_CTL_GRP_DDRPKE
//CLOCK:
MXC_DCD_ITEM(3,0x020e0588 , 0x00000030) // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
MXC_DCD_ITEM(4,0x020e0594 , 0x00000030) // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1
//ADDRESS:
MXC_DCD_ITEM(5,0x020e056c , 0x00000030) // IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
MXC_DCD_ITEM(6,0x020e0578 , 0x00000030) // IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
MXC_DCD_ITEM(7,0x020e074c , 0x00000030) // IOMUXC_SW_PAD_CTL_GRP_ADDDS
//Control:
MXC_DCD_ITEM(8,0x020e057c , 0x00000030) // IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET
MXC_DCD_ITEM(9,0x020e058c , 0x00000000) // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS
MXC_DCD_ITEM(10,0x020e059c , 0x00000030) // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
MXC_DCD_ITEM(11,0x020e05a0 , 0x00000030) // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
MXC_DCD_ITEM(12,0x020e078c , 0x00000030) // IOMUXC_SW_PAD_CTL_GRP_CTLDS
//Data Strobes:
MXC_DCD_ITEM(13,0x020e0750 , 0x00020000) // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
MXC_DCD_ITEM(14,0x020e05a8 , 0x00000030) // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
MXC_DCD_ITEM(15,0x020e05b0 , 0x00000030) // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
MXC_DCD_ITEM(16,0x020e0524 , 0x00000030) // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
MXC_DCD_ITEM(17,0x020e051c , 0x00000030) // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
MXC_DCD_ITEM(18,0x020e0518 , 0x00000030) // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4
MXC_DCD_ITEM(19,0x020e050c , 0x00000030) // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5
MXC_DCD_ITEM(20,0x020e05b8 , 0x00000030) // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6
MXC_DCD_ITEM(21,0x020e05c0 , 0x00000030) // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7
//Data:
MXC_DCD_ITEM(22,0x020e0774 , 0x00020000) // IOMUXC_SW_PAD_CTL_GRP_DDRMODE
MXC_DCD_ITEM(23,0x020e0784 , 0x00000030) // IOMUXC_SW_PAD_CTL_GRP_B0DS
MXC_DCD_ITEM(24,0x020e0788 , 0x00000030) // IOMUXC_SW_PAD_CTL_GRP_B1DS
MXC_DCD_ITEM(25,0x020e0794 , 0x00000030) // IOMUXC_SW_PAD_CTL_GRP_B2DS
MXC_DCD_ITEM(26,0x020e079c , 0x00000030) // IOMUXC_SW_PAD_CTL_GRP_B3DS
MXC_DCD_ITEM(27,0x020e07a0 , 0x00000030) // IOMUXC_SW_PAD_CTL_GRP_B4DS
MXC_DCD_ITEM(28,0x020e07a4 , 0x00000030) // IOMUXC_SW_PAD_CTL_GRP_B5DS
MXC_DCD_ITEM(29,0x020e07a8 , 0x00000030) // IOMUXC_SW_PAD_CTL_GRP_B6DS
MXC_DCD_ITEM(30,0x020e0748 , 0x00000030) // IOMUXC_SW_PAD_CTL_GRP_B7DS
MXC_DCD_ITEM(31,0x020e05ac , 0x00000030) // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
MXC_DCD_ITEM(32,0x020e05b4 , 0x00000030) // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
MXC_DCD_ITEM(33,0x020e0528 , 0x00000030) // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
MXC_DCD_ITEM(34,0x020e0520 , 0x00000030) // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
MXC_DCD_ITEM(35,0x020e0514 , 0x00000030) // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4
MXC_DCD_ITEM(36,0x020e0510 , 0x00000030) // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5
MXC_DCD_ITEM(37,0x020e05bc , 0x00000030) // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6
MXC_DCD_ITEM(38,0x020e05c4 , 0x00000030) // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7
//,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
// DDR Controller Registers
//,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
// Manufacturer: Samsung
// Device Part Number: K4B4G1646B HCK0
// Clock Freq.: 528MHz
// Density per CS in Gb: 16
// Chip Selects used: 1
// Number of Banks: 8
// Row address: 15
// Column address: 10
// Data bus width 64
// MMDC_P0_BASE_ADDR = 0x021b 0000
//,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
MXC_DCD_ITEM(39,0x021b001c , 0x00008000) //MMDC0_MDSCR, set the Configuration request bit during MMDC set up
//,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
// Calibration setup.
//,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
MXC_DCD_ITEM(40,0x021b0800 , 0xA1390003) // DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration.
// For target board, may need to run write leveling calibration to fine tune these settings.
MXC_DCD_ITEM(41,0x021b080c ,0x00000000)
MXC_DCD_ITEM(42,0x021b0810 , 0x00000000)
MXC_DCD_ITEM(43,0x021b480c ,0x00000000)
MXC_DCD_ITEM(44,0x021b4810 , 0x00000000)
////Read DQS Gating calibration
MXC_DCD_ITEM(45,0x021b083c , 0x00000000) // MPDGCTRL0 PHY0
MXC_DCD_ITEM(46,0x021b0840 , 0x00000000) // MPDGCTRL1 PHY0
MXC_DCD_ITEM(47,0x021b483c , 0x00000000) // MPDGCTRL0 PHY1
MXC_DCD_ITEM(48,0x021b4840 , 0x00000000) // MPDGCTRL1 PHY1
//Read calibration
MXC_DCD_ITEM(49,0x021b0848 , 0x40404040) // MPRDDLCTL PHY0
MXC_DCD_ITEM(50,0x021b4848 , 0x40404040) // MPRDDLCTL PHY1
//Write calibration
MXC_DCD_ITEM(51,0x021b0850 , 0x40404040) // MPWRDLCTL PHY0
MXC_DCD_ITEM(52,0x021b4850 , 0x40404040) // MPWRDLCTL PHY1
//read data bit delay: (3 is the reccommended default value, although out of reset value is 0)
MXC_DCD_ITEM(53,0x021b081c , 0x33333333) // DDR_PHY_P0_MPREDQBY0DL3
MXC_DCD_ITEM(54,0x021b0820 , 0x33333333) // DDR_PHY_P0_MPREDQBY1DL3
MXC_DCD_ITEM(55,0x021b0824 , 0x33333333) // DDR_PHY_P0_MPREDQBY2DL3
MXC_DCD_ITEM(56,0x021b0828 , 0x33333333) // DDR_PHY_P0_MPREDQBY3DL3
MXC_DCD_ITEM(57,0x021b481c , 0x33333333) // DDR_PHY_P1_MPREDQBY0DL3
MXC_DCD_ITEM(58,0x021b4820 , 0x33333333) // DDR_PHY_P1_MPREDQBY1DL3
MXC_DCD_ITEM(59,0x021b4824 , 0x33333333) // DDR_PHY_P1_MPREDQBY2DL3
MXC_DCD_ITEM(60,0x021b4828 , 0x33333333) // DDR_PHY_P1_MPREDQBY3DL3
//For i.mx6qd parts of versions A & B (v1.0, v1.1), uncomment the following lines. For version C (v1.2), keep commented
// 0x021b08c0 , 0x24911492 // fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6
// 0x021b48c0 , 0x24911492
// Complete calibration by forced measurement:
MXC_DCD_ITEM(61,0x021b08b8 , 0x00000800) // DDR_PHY_P0_MPMUR0, frc_msr
MXC_DCD_ITEM(62,0x021b48b8 , 0x00000800) // DDR_PHY_P0_MPMUR0, frc_msr
//,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
// Calibration setup end
//,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
//MMDC init:
MXC_DCD_ITEM(63,0x021b0004 , 0x00020036) // MMDC0_MDPDC
MXC_DCD_ITEM(64,0x021b0008 , 0x09444040) // MMDC0_MDOTC
MXC_DCD_ITEM(65,0x021b000c , 0x898E7958) // MMDC0_MDCFG0
MXC_DCD_ITEM(66,0x021b0010 , 0x48DB8F64) // MMDC0_MDCFG1
MXC_DCD_ITEM(67,0x021b0014 , 0x01FF00DB) // MMDC0_MDCFG2
//MDMISC: RALAT kept to the high level of 5.
//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:
//a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3
//b. Small performence improvment
MXC_DCD_ITEM(68,0x021b0018 , 0x00011740) // MMDC0_MDMISC
MXC_DCD_ITEM(69,0x021b001c , 0x00008000) // MMDC0_MDSCR, set the Configuration request bit during MMDC set up
MXC_DCD_ITEM(70,0x021b002c , 0x000026D2) // MMDC0_MDRWD
MXC_DCD_ITEM(71,0x021b0030 , 0x008E1023) // MMDC0_MDOR
MXC_DCD_ITEM(72,0x021b0040 , 0x00000047) // Chan0 CS0_END
MXC_DCD_ITEM(73,0x021b0000 , 0x841A0000) // MMDC0_MDCTL
//Mode register writes
MXC_DCD_ITEM(74,0x021b001c , 0x02088032) // MMDC0_MDSCR, MR2 write, CS0
MXC_DCD_ITEM(75,0x021b001c , 0x00008033) // MMDC0_MDSCR, MR3 write, CS0
//MXC_DCD_ITEM(76,0x021b001c , 0x00048031) // MMDC0_MDSCR, MR1 write, CS0
MXC_DCD_ITEM(76,0x021b001c , 0x00448031) // MMDC0_MDSCR, MR1 write, CS0
MXC_DCD_ITEM(77,0x021b001c , 0x19708030) // MMDC0_MDSCR, MR0write, CS0
MXC_DCD_ITEM(78,0x021b001c , 0x04008040) // MMDC0_MDSCR, ZQ calibration command sent to device on CS0
MXC_DCD_ITEM(79,0x021b0020 , 0x00007800) // MMDC0_MDREF
//MXC_DCD_ITEM(80,0x021b0818 , 0x00022227) // DDR_PHY_P0_MPODTCTRL
//MXC_DCD_ITEM(81,0x021b4818 , 0x00022227) // DDR_PHY_P1_MPODTCTRL
MXC_DCD_ITEM(80,0x021b0818 , 0x00033337) // DDR_PHY_P0_MPODTCTRL
MXC_DCD_ITEM(81,0x021b4818 , 0x00033337) // DDR_PHY_P1_MPODTCTRL
MXC_DCD_ITEM(82,0x021b0004 , 0x00025576) // MMDC0_MDPDC now SDCTL power down enabled
MXC_DCD_ITEM(83,0x021b0404 , 0x00011006) // MMDC0_MAPSR ADOPT power down enabled, MMDC will enter automatically to self-refresh while the number of idle cycle reached.
MXC_DCD_ITEM(84,0x021b001c , 0x00000000) // MMDC0_MDSCR, clear this register (especially the configuration bit as initialization is complete)
填写到flash_header.S，但是实际运行中板并没有启动成功，也没有任何打印信息。
不知道哪一个参数设置的问题，求解
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