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-- Company:
-- Engineer:
--
-- Create Date: 16:57:10 12/02/2014
-- Design Name:
-- Module Name: fir_total - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity fir_total is
port (clk : in std_logic;
reset: in std_logic;
x: in std_logic_vector(7 downto 0);
y: out std_logic_vector(14 downto 0)
);
end fir_total;
architecture Behavioral of fir_total is
signal x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15: std_logic_vector(7 downto 0);
signal p0,p1,p2,p3,p4,p5,p6,p7:integer;
signal sum: integer;
-- coefficient
constant h0: integer:=-831;
constant h1: integer:=-2102;
constant h2: integer:=918;
constant h3: integer:=-372;
constant h4: integer:=0;
constant h5: integer:=242;
constant h6: integer:=-278;
constant h7: integer:=118;
constant h8: integer:=118;
constant h9: integer:=-278;
constant h10: integer:=242;
constant h11: integer:=0;
constant h12: integer:=-372;
constant h13: integer:=918;
constant h14: integer:=-2102;
constant h15: integer:=-831;
begin
process (clk)
begin
if rising_edge(clk) then
if reset='1' then
x15 <=( others =>'0');
x14 <=( others =>'0');
x13 <=( others =>'0');
x12 <=( others =>'0');
x11 <=( others =>'0');
x10 <=( others =>'0');
x9 <=( others =>'0');
x8 <=( others =>'0');
x7 <=( others =>'0');
x6 <=( others =>'0');
x5 <=( others =>'0');
x4 <=( others =>'0');
x3 <=( others =>'0');
x2 <=( others =>'0');
x1 <=( others =>'0');
x0 <=( others =>'0');
else
x15 <= x14;
x14 <= x13;
x13 <= x12;
x12 <= x11;
x11 <= x10;
x10 <= x9;
x9 <= x8;
x8 <= x7;
x7 <= x6;
x6 <= x5;
x5 <= x4;
x4 <= x3;
x3 <= x2;
x2 <= x1;
x1 <= x0;
x0 <= x;
end if;
end if;
end process;
p0 <= (conv_integer(x0)+conv_integer(x15))*h0;
p1 <= (conv_integer(x1)+conv_integer(x14))*h1;
p2 <= (conv_integer(x2)+conv_integer(x13))*h2;
p3 <= (conv_integer(x3)+conv_integer(x12))*h3;
p4 <= (conv_integer(x4)+conv_integer(x11))*h4;
p5 <= (conv_integer(x5)+conv_integer(x10))*h5;
p6 <= (conv_integer(x6)+conv_integer(x9))*h6;
p7 <= (conv_integer(x7)+conv_integer(x8))*h7;
sum <= p0+p1+p2+p3+p4+p5+p6+p7;
y <= conv_std_logic_vector(sum,15);
end Behavioral;
--signal count: natural range 0 to 4;
--signal enable: std_logic;
-- process (clk,reset)
-- begin
-- if reset='1' then
-- count <= 0;
-- elsif rising_edge(clk) and (enable='0') then
-- count <= count +1;
-- end if;
-- end process;
--
-- enable <= '1' when (count=4)
-- else '0';
--
-- process(enable)
-- begin
-- if enable ='1' then
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我设计的fir滤波器，将数据在matlab里面显示，反而高频率的信号的输出好过低频率的 |
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