fans倒是不错，但是只要**说道理，又有何妨?

1万 · 2009-1-8 13:04

PIC的IO速度远比CM3快

PIC32 Architecture Overview第11页最后几句：

In the beginning, we noted that the I/O PORT peripherals are connected to the SYSCLK bus. This
means that with the help of the INV registers, you can toggle any general purpose I/O pin at the
SYSCLK speed!

1万 · 2009-1-8 13:06

Note that the I/O PORT modules are also on the SYSCLK bus. This means that
CPU can access I/O PORTs at max operating frequency

1万 · 2009-1-8 13:18

In the previous slide, we learned that priority level 7 vectors get the highest priority.
In addition to that, the priority 7 vectors also get a dedicated shadow register set. In
normal operation when the CPU is executing at priority 6 or lower, the CPU
operates on a primary register set. But when a priority 7 interrupt occurs, the
interrupt controller automatically switches to the shadow set and jumps to the
appropriate vector. With the dedicated shadow set, the priority 7 interrupt offers
faster interrupt response as compared to other priority interrupts. The reason for
this is that when the priority 7 interrupt occurs, the application does not have to save
the entire register set context. Instead, it only needs to save a few critical registers
and start executing the user interrupt handler. Similarly, when the priority 7
interrupt handler finishes its task, the application does not have to restore the full
context either. It only needs to perform few steps and immediately return to the
previous execution state.

从简介来看PIC32的中断延迟性能应该不错，应该也就是保存几个critical registers所需时钟周期。可惜没有看到具体的中断延迟数据。

1万 · 2009-1-8 18:37

PIC32的IO速度远比CM3快

PIC32 Architecture Overview第11页最后几句：

In the beginning, we noted that the I/O PORT peripherals are connected to the SYSCLK bus. This
means that with the help of the INV registers, you can toggle any general purpose I/O pin at the
speed!

IC32 Architecture Overview第6页最后几句

Note that the I/O PORT modules are also on the SYSCLK bus. This means that
CPU can access I/O PORTs at max operating frequency

PIC32底IO速度同SYSCLK速度,
远比CM3快

1万 · 2009-1-8 22:50

PIC32手册第二章MCU 2.8节SET/CLEAR/INVERT介绍了,

置位,清零,翻转指令实现对外设寄存器的单周期原子操作:

2.8 SET/CLEAR/INVERT
To provide single-cycle bit operations on peripherals, the registers in the peripheral units can be
accessed in three different ways depending on peripheral addresses. Each register has four different
addresses. Although the four different addresses appear as different registers, they are
really just four different methods to address the same physical register.

The base register address provides normal Read/Write access, the other three provide special
write-only functions.
1. Normal access
2. Set bit atomic RMW access
3. Clear bit atomic RMW access
4. Invert bit atomic RMW access
Peripheral reads must occur from the base address of each peripheral register. Reading from a
set/clear/invert address has an undefined meaning, and may be different for each peripheral.
Writing to the base address writes an entire value to the peripheral register. All bits are written.
For example, assume a register contains 0xaaaa5555 before a write of 0x000000ff. After the
write, the register will contain 0x000000ff (assuming that all bits are R/W bits).
Writing to the Set address for any peripheral register causes only the bits written as ‘1’s to be set
in the destination register. For example, assume that a register contains 0xaaaa5555 before a
write of 0x000000ff to the set register address. After the write to the Set register address, the
value of the peripheral register will contain 0xaaaa55ff.
Writing to the Clear address for any peripheral register causes only the bits written as ‘1’s to be
cleared to ‘0’s in the destination register. For example, assume that a register contains
0xaaaa5555 before a write of 0x000000ff to the Clear register address. After the write to the
Clear register address, the value of the peripheral register will contain 0xaaaa5500.
Writing to the Invert address for any peripheral register causes only the bits written as ‘1’s to be
inverted, or toggled, in the destination register. For example, assume that a register contains
0xaaaa5555 before a write of 0x000000ff to the invert register address. After the write to the
Invert register, the value of the peripheral register will contain 0xaaaa55aa.

1万 · 2009-1-8 23:06

使用Dedicated General Purpose Register Set的情况下:

中断现场保护
rdpgpr sp, sp
mfc0 k0, Cause
mfc0 k1, EPC
srl k0, k0, 0xa
addiu sp, sp, -76
sw k1, 0(sp)
mfc0 k1, Status
sw k1, 4(sp)
ins k1, k0, 10, 6
ins k1,zero, 1, 4
mtc0 k1, Status
addu s8, sp, zero

12条指令,12个时钟周期

中断现场恢复:
addu sp, s8, zero
di
lw k0, 0(sp)
mtc0 k0, EPC
lw k0, 4(sp)
mtc0 k0, Status
eret

7条指令.

PIC32和CM3的中断延迟差不多

1万 · 2009-1-9 08:46

12.2.1 CLR, SET AND INV REGISTERS（PIC32 数据手册IO部分）
Every I/O module register has a corresponding CLR
(clear), SET (set) and INV (invert) register designed to
provide fast atomic bit manipulations. As the name of
the register implies, a value written to a SET, CLR or
INV register effectively performs the implied operation,
but only on the corresponding base register and only
bits specified as ‘1’ are modified. Bits specified as ‘0’
are not modified.
Reading SET, CLR and INV registers returns undefined
values. To see the affects of a write operation to a SET,
CLR or INV register, the base register must be read.
To set PORTC bit 0, write to the LATSET register:
LATCSET = 0x0001;
To clear PORTC bit 0, write to the LATCLR register:
LATCCLR = 0x0001;
To toggle PORTC bit 0, write to the LATINV register:
LATCINV = 0x0001;

IO输出就是一条对相关IO寄存器的置位，清零，翻转别名寄存器的写操作，
而IO寄存器是接在SYSCLK总线上的。

PIC32的IO当然远比CM3快。

只看该作者 · 2009-1-9 09:24

一个是PIC fans？一个是CM3 fans?

1万 · 2009-1-9 09:33

fans倒是不错，但是只要坚持说道理，又有何妨?

1万 · 2009-1-9 10:07

sw $a0, 0($s0) /* clear specified bits */

看看是不是和2812相似呢？

反正是远比CM3快

1万 · 2009-1-9 10:18

TMS320F2812:

MOVW DP,#0x01BF
ORR @1,#0x2000

PIC32:
la $s0, LATACLR
sw $a0, 0($s0) /* clear specified bits */

其实严格的说都不是一条指令，都包括一条取外设寄存器地址的指令，

因为外设寄存器比较不是内核寄存器。

当然如果连续操作，都是一条指令.

应该都比CM3快不少。

还有一点就是CM3的

LDR R0,[xxxx]
STR R0,[xxxx]

可能都不一定是一个时钟周期。

PIC32的IO寄存器是接在SYSCLK上，确保了其对IO寄存器的操作是1个时钟周期

1万 · 2009-1-9 10:48

其实这还牵涉到IO模块是否接在SYSCLK总线上。
不光是指令数目的问题。

以NXP的LPC2000 ARM7为例:

如果用普通IO：
    94:         IOCLR |= SPI_595_LAT;
0x00000D20  E59F2190  LDR       R2,[PC,#0x0190]
0x00000D24  E592200C  LDR       R2,[R2,#0x000C]
0x00000D28  E3822502  ORR       R2,R2,#0x00800000
0x00000D2C  E59F3184  LDR       R3,[PC,#0x0184]
0x00000D30  E583200C  STR       R2,[R3,#0x000C]

用快速FIO：
    73:         FIODIR |= SPIOUT;
0x00000DE4  E59F039C  LDR       R0,[PC,#0x039C]
0x00000DE8  E5900000  LDR       R0,[R0]
0x00000DEC  E3800040  ORR       R0,R0,#0x00000040
0x00000DF0  E59F1390  LDR       R1,[PC,#0x0390]
0x00000DF4  E5810000  STR       R0,[R1]

指令数目一样，但是普通IO绝对不是5个指令周期,

快速FIO，好像也只能提供最大17.5MHz的IO操作速度

但是快速FIO提供了比普通IO好的多的速度,
因为快速FIO接在高速总线上的，
二者的速度差别很大。

所以，确保IO模块都是接在SYSCLK总线上，数指令个数才有意义

1万 · 2009-1-9 10:52

如果IO模块接在SYSCLK总线上，对IO的连续操作将是单周期，

偶尔操作慢一点，

这牵涉到取IO寄存器地址，以及取立即数。

1万 · 2009-1-9 11:12

方法：
1.设置好定时器，让定时器运行

2.测试伪代码:

temp1 = Rtime；// 设Rtime是定时器的计数寄存器
IO 操作1；
IO 操作2
temp2 ＝ Rtime；

if(temp2 > temp1)
time ＝ temp2－temp1；
else
time = temp2 + MAX_TIME -time1;//MAX_TIME定时计数器满值

time值减去读取定时器的计数寄存器的两条指令的时钟数目就是IO操作的时钟数目。

当然必须是实际硬件才可靠，软仿不一定。

1万 · 2009-1-9 12:24

CM3的GPIO果然是桥接的，速度不会快

1万 · 2009-1-9 12:39

看看PIC32，IO接在系统时钟总线，其他外设接在外设总线

2812 IO接在外设总线，CM3接在APB2总线，都不是接在系统时钟总线上，

速度能一样吗？

1万 · 2009-1-9 14:07

CM3接在APB2总线？谁说的？GPIO接在CM3的AHB总线上就不行吗？

只看该作者 · 2009-1-9 14:22

我8bit还没搞醒豁

又来32bit的了。

哎.整不归依.

1万 · 2009-1-9 19:27

APB2是可以设置为SYSCLK同频,但这样将使链接到APB2总线上的其他外设的以高频工作,增加系统功耗.

CM3的IO操作速度慢的还有一个原因就是LDA,STA指令周期,不是单周期,

好像不是2周期,就是3周期.

LDA R0, [PC,#0x0BC]
MOVS R1 #0x1
STR R1, [R0,#0]

可是比PIC32慢不少

只看该作者 · 2009-1-14 13:19

争论半天被人搞陷阱了快了就好么
M4K支持每个中断有中断入口么，不然增多很多入口判断
另外就是编译效率看看PIC32的ucos移植比CORTEX的多出一倍不止

fans倒是不错，但是只要**说道理，又有何妨?

PIC的IO速度远比CM3快

IC32 Architecture Overview第6页最后几句

从简介来看PIC32的中断延迟性能应该不错

PIC32底IO速度

PIC32手册第二章MCU 2.8节SET/CLEAR/INVERT

PIC32的中断延迟和CM3差不多

来点带例子的举证

两位真有兴致~呵呵

fans倒是不错，但是只要**说道理，又有何妨?

清零指令

比较

其实这还牵涉到IO模块是否接在SYSCLK总线上

如果IO模块接在SYSCLK总线上，对IO的连续操作将是单周期

其实有人如果感兴趣，可以测一下

CM3的GPIO果然是桥接的，速度不会快

看看PIC32，IO接在系统时钟总线，其他外设接在外设总线

CM3接在APB2总线

靠,看得我眼睛花

APB2是可以设置为SYSCLK同频

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