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machunshui 发表于 2009-1-8 13:04 | 显示全部楼层

PIC的IO速度远比CM3快

PIC的IO速度远比CM3快<br /><br />PIC32&nbsp;Architecture&nbsp;Overview第11页最后几句：<br /><br /><br />In&nbsp;the&nbsp;beginning,&nbsp;we&nbsp;noted&nbsp;that&nbsp;the&nbsp;I/O&nbsp;PORT&nbsp;peripherals&nbsp;are&nbsp;connected&nbsp;to&nbsp;the&nbsp;SYSCLK&nbsp;bus.&nbsp;This<br />means&nbsp;that&nbsp;with&nbsp;the&nbsp;help&nbsp;of&nbsp;the&nbsp;INV&nbsp;registers,&nbsp;you&nbsp;can&nbsp;toggle&nbsp;any&nbsp;general&nbsp;purpose&nbsp;I/O&nbsp;pin&nbsp;at&nbsp;the<br />SYSCLK&nbsp;speed!
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machunshui 发表于 2009-1-8 13:06 | 显示全部楼层

IC32 Architecture Overview第6页最后几句

Note&nbsp;that&nbsp;the&nbsp;I/O&nbsp;PORT&nbsp;modules&nbsp;are&nbsp;also&nbsp;on&nbsp;the&nbsp;SYSCLK&nbsp;bus.&nbsp;This&nbsp;means&nbsp;that<br />CPU&nbsp;can&nbsp;access&nbsp;I/O&nbsp;PORTs&nbsp;at&nbsp;max&nbsp;operating&nbsp;frequency
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machunshui 发表于 2009-1-8 13:18 | 显示全部楼层

从简介来看PIC32的中断延迟性能应该不错

In&nbsp;the&nbsp;previous&nbsp;slide,&nbsp;we&nbsp;learned&nbsp;that&nbsp;priority&nbsp;level&nbsp;7&nbsp;vectors&nbsp;get&nbsp;the&nbsp;highest&nbsp;priority.<br />In&nbsp;addition&nbsp;to&nbsp;that,&nbsp;the&nbsp;priority&nbsp;7&nbsp;vectors&nbsp;also&nbsp;get&nbsp;a&nbsp;dedicated&nbsp;shadow&nbsp;register&nbsp;set.&nbsp;In<br />normal&nbsp;operation&nbsp;when&nbsp;the&nbsp;CPU&nbsp;is&nbsp;executing&nbsp;at&nbsp;priority&nbsp;6&nbsp;or&nbsp;lower,&nbsp;the&nbsp;CPU<br />operates&nbsp;on&nbsp;a&nbsp;primary&nbsp;register&nbsp;set.&nbsp;But&nbsp;when&nbsp;a&nbsp;priority&nbsp;7&nbsp;interrupt&nbsp;occurs,&nbsp;the<br />interrupt&nbsp;controller&nbsp;automatically&nbsp;switches&nbsp;to&nbsp;the&nbsp;shadow&nbsp;set&nbsp;and&nbsp;jumps&nbsp;to&nbsp;the<br />appropriate&nbsp;vector.&nbsp;With&nbsp;the&nbsp;dedicated&nbsp;shadow&nbsp;set,&nbsp;the&nbsp;priority&nbsp;7&nbsp;interrupt&nbsp;offers<br />faster&nbsp;interrupt&nbsp;response&nbsp;as&nbsp;compared&nbsp;to&nbsp;other&nbsp;priority&nbsp;interrupts.&nbsp;The&nbsp;reason&nbsp;for<br />this&nbsp;is&nbsp;that&nbsp;when&nbsp;the&nbsp;priority&nbsp;7&nbsp;interrupt&nbsp;occurs,&nbsp;the&nbsp;application&nbsp;does&nbsp;not&nbsp;have&nbsp;to&nbsp;save<br />the&nbsp;entire&nbsp;register&nbsp;set&nbsp;context.&nbsp;Instead,&nbsp;it&nbsp;only&nbsp;needs&nbsp;to&nbsp;save&nbsp;a&nbsp;few&nbsp;critical&nbsp;registers<br />and&nbsp;start&nbsp;executing&nbsp;the&nbsp;user&nbsp;interrupt&nbsp;handler.&nbsp;Similarly,&nbsp;when&nbsp;the&nbsp;priority&nbsp;7<br />interrupt&nbsp;handler&nbsp;finishes&nbsp;its&nbsp;task,&nbsp;the&nbsp;application&nbsp;does&nbsp;not&nbsp;have&nbsp;to&nbsp;restore&nbsp;the&nbsp;full<br />context&nbsp;either.&nbsp;It&nbsp;only&nbsp;needs&nbsp;to&nbsp;perform&nbsp;few&nbsp;steps&nbsp;and&nbsp;immediately&nbsp;return&nbsp;to&nbsp;the<br />previous&nbsp;execution&nbsp;state.<br /><br />从简介来看PIC32的中断延迟性能应该不错，应该也就是保存几个critical&nbsp;registers所需时钟周期。可惜没有看到具体的中断延迟数据。
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machunshui 发表于 2009-1-8 18:37 | 显示全部楼层

PIC32底IO速度

PIC32的IO速度远比CM3快<br /><br />PIC32&nbsp;Architecture&nbsp;Overview第11页最后几句：<br /><br /><br />In&nbsp;the&nbsp;beginning,&nbsp;we&nbsp;noted&nbsp;that&nbsp;the&nbsp;I/O&nbsp;PORT&nbsp;peripherals&nbsp;are&nbsp;connected&nbsp;to&nbsp;the&nbsp;SYSCLK&nbsp;bus.&nbsp;This<br />means&nbsp;that&nbsp;with&nbsp;the&nbsp;help&nbsp;of&nbsp;the&nbsp;INV&nbsp;registers,&nbsp;you&nbsp;can&nbsp;toggle&nbsp;any&nbsp;general&nbsp;purpose&nbsp;I/O&nbsp;pin&nbsp;at&nbsp;the<br />&nbsp;speed!<br /><br />IC32&nbsp;Architecture&nbsp;Overview第6页最后几句<br /><br />Note&nbsp;that&nbsp;the&nbsp;I/O&nbsp;PORT&nbsp;modules&nbsp;are&nbsp;also&nbsp;on&nbsp;the&nbsp;SYSCLK&nbsp;bus.&nbsp;This&nbsp;means&nbsp;that<br />CPU&nbsp;can&nbsp;access&nbsp;I/O&nbsp;PORTs&nbsp;at&nbsp;max&nbsp;operating&nbsp;frequency<br /><br />PIC32底IO速度同SYSCLK速度,<br />远比CM3快
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machunshui 发表于 2009-1-8 22:50 | 显示全部楼层

PIC32手册第二章MCU 2.8节SET/CLEAR/INVERT

PIC32手册第二章MCU&nbsp;2.8节SET/CLEAR/INVERT介绍了,<br /><br />置位,清零,翻转指令实现对外设寄存器的单周期原子操作:<br /><br />2.8&nbsp;SET/CLEAR/INVERT<br />To&nbsp;provide&nbsp;single-cycle&nbsp;bit&nbsp;operations&nbsp;on&nbsp;peripherals,&nbsp;the&nbsp;registers&nbsp;in&nbsp;the&nbsp;peripheral&nbsp;units&nbsp;can&nbsp;be<br />accessed&nbsp;in&nbsp;three&nbsp;different&nbsp;ways&nbsp;depending&nbsp;on&nbsp;peripheral&nbsp;addresses.&nbsp;Each&nbsp;register&nbsp;has&nbsp;four&nbsp;different<br />addresses.&nbsp;Although&nbsp;the&nbsp;four&nbsp;different&nbsp;addresses&nbsp;appear&nbsp;as&nbsp;different&nbsp;registers,&nbsp;they&nbsp;are<br />really&nbsp;just&nbsp;four&nbsp;different&nbsp;methods&nbsp;to&nbsp;address&nbsp;the&nbsp;same&nbsp;physical&nbsp;register.<br /><br />The&nbsp;base&nbsp;register&nbsp;address&nbsp;provides&nbsp;normal&nbsp;Read/Write&nbsp;access,&nbsp;the&nbsp;other&nbsp;three&nbsp;provide&nbsp;special<br />write-only&nbsp;functions.<br />1.&nbsp;Normal&nbsp;access<br />2.&nbsp;Set&nbsp;bit&nbsp;atomic&nbsp;RMW&nbsp;access<br />3.&nbsp;Clear&nbsp;bit&nbsp;atomic&nbsp;RMW&nbsp;access<br />4.&nbsp;Invert&nbsp;bit&nbsp;atomic&nbsp;RMW&nbsp;access<br />Peripheral&nbsp;reads&nbsp;must&nbsp;occur&nbsp;from&nbsp;the&nbsp;base&nbsp;address&nbsp;of&nbsp;each&nbsp;peripheral&nbsp;register.&nbsp;Reading&nbsp;from&nbsp;a<br />set/clear/invert&nbsp;address&nbsp;has&nbsp;an&nbsp;undefined&nbsp;meaning,&nbsp;and&nbsp;may&nbsp;be&nbsp;different&nbsp;for&nbsp;each&nbsp;peripheral.<br />Writing&nbsp;to&nbsp;the&nbsp;base&nbsp;address&nbsp;writes&nbsp;an&nbsp;entire&nbsp;value&nbsp;to&nbsp;the&nbsp;peripheral&nbsp;register.&nbsp;All&nbsp;bits&nbsp;are&nbsp;written.<br />For&nbsp;example,&nbsp;assume&nbsp;a&nbsp;register&nbsp;contains&nbsp;0xaaaa5555&nbsp;before&nbsp;a&nbsp;write&nbsp;of&nbsp;0x000000ff.&nbsp;After&nbsp;the<br />write,&nbsp;the&nbsp;register&nbsp;will&nbsp;contain&nbsp;0x000000ff&nbsp;(assuming&nbsp;that&nbsp;all&nbsp;bits&nbsp;are&nbsp;R/W&nbsp;bits).<br />Writing&nbsp;to&nbsp;the&nbsp;Set&nbsp;address&nbsp;for&nbsp;any&nbsp;peripheral&nbsp;register&nbsp;causes&nbsp;only&nbsp;the&nbsp;bits&nbsp;written&nbsp;as&nbsp;‘1’s&nbsp;to&nbsp;be&nbsp;set<br />in&nbsp;the&nbsp;destination&nbsp;register.&nbsp;For&nbsp;example,&nbsp;assume&nbsp;that&nbsp;a&nbsp;register&nbsp;contains&nbsp;0xaaaa5555&nbsp;before&nbsp;a<br />write&nbsp;of&nbsp;0x000000ff&nbsp;to&nbsp;the&nbsp;set&nbsp;register&nbsp;address.&nbsp;After&nbsp;the&nbsp;write&nbsp;to&nbsp;the&nbsp;Set&nbsp;register&nbsp;address,&nbsp;the<br />value&nbsp;of&nbsp;the&nbsp;peripheral&nbsp;register&nbsp;will&nbsp;contain&nbsp;0xaaaa55ff.<br />Writing&nbsp;to&nbsp;the&nbsp;Clear&nbsp;address&nbsp;for&nbsp;any&nbsp;peripheral&nbsp;register&nbsp;causes&nbsp;only&nbsp;the&nbsp;bits&nbsp;written&nbsp;as&nbsp;‘1’s&nbsp;to&nbsp;be<br />cleared&nbsp;to&nbsp;‘0’s&nbsp;in&nbsp;the&nbsp;destination&nbsp;register.&nbsp;For&nbsp;example,&nbsp;assume&nbsp;that&nbsp;a&nbsp;register&nbsp;contains<br />0xaaaa5555&nbsp;before&nbsp;a&nbsp;write&nbsp;of&nbsp;0x000000ff&nbsp;to&nbsp;the&nbsp;Clear&nbsp;register&nbsp;address.&nbsp;After&nbsp;the&nbsp;write&nbsp;to&nbsp;the<br />Clear&nbsp;register&nbsp;address,&nbsp;the&nbsp;value&nbsp;of&nbsp;the&nbsp;peripheral&nbsp;register&nbsp;will&nbsp;contain&nbsp;0xaaaa5500.<br />Writing&nbsp;to&nbsp;the&nbsp;Invert&nbsp;address&nbsp;for&nbsp;any&nbsp;peripheral&nbsp;register&nbsp;causes&nbsp;only&nbsp;the&nbsp;bits&nbsp;written&nbsp;as&nbsp;‘1’s&nbsp;to&nbsp;be<br />inverted,&nbsp;or&nbsp;toggled,&nbsp;in&nbsp;the&nbsp;destination&nbsp;register.&nbsp;For&nbsp;example,&nbsp;assume&nbsp;that&nbsp;a&nbsp;register&nbsp;contains<br />0xaaaa5555&nbsp;before&nbsp;a&nbsp;write&nbsp;of&nbsp;0x000000ff&nbsp;to&nbsp;the&nbsp;invert&nbsp;register&nbsp;address.&nbsp;After&nbsp;the&nbsp;write&nbsp;to&nbsp;the<br />Invert&nbsp;register,&nbsp;the&nbsp;value&nbsp;of&nbsp;the&nbsp;peripheral&nbsp;register&nbsp;will&nbsp;contain&nbsp;0xaaaa55aa.
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machunshui 发表于 2009-1-8 23:06 | 显示全部楼层

PIC32的中断延迟和CM3差不多

使用Dedicated&nbsp;General&nbsp;Purpose&nbsp;Register&nbsp;Set的情况下:<br /><br />中断现场保护<br />rdpgpr&nbsp;sp,&nbsp;sp<br />mfc0&nbsp;k0,&nbsp;Cause<br />mfc0&nbsp;k1,&nbsp;EPC<br />srl&nbsp;k0,&nbsp;k0,&nbsp;0xa<br />addiu&nbsp;sp,&nbsp;sp,&nbsp;-76<br />sw&nbsp;k1,&nbsp;0(sp)<br />mfc0&nbsp;k1,&nbsp;Status<br />sw&nbsp;k1,&nbsp;4(sp)<br />ins&nbsp;k1,&nbsp;k0,&nbsp;10,&nbsp;6<br />ins&nbsp;k1,zero,&nbsp;1,&nbsp;4<br />mtc0&nbsp;k1,&nbsp;Status<br />addu&nbsp;s8,&nbsp;sp,&nbsp;zero<br /><br />12条指令,12个时钟周期<br /><br />中断现场恢复:<br />addu&nbsp;sp,&nbsp;s8,&nbsp;zero<br />di<br />lw&nbsp;k0,&nbsp;0(sp)<br />mtc0&nbsp;k0,&nbsp;EPC<br />lw&nbsp;k0,&nbsp;4(sp)<br />mtc0&nbsp;k0,&nbsp;Status<br />eret<br /><br />7条指令.<br /><br /><br />PIC32和CM3的中断延迟差不多
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machunshui 发表于 2009-1-9 08:46 | 显示全部楼层

来点带例子的举证

12.2.1&nbsp;CLR,&nbsp;SET&nbsp;AND&nbsp;INV&nbsp;REGISTERS（PIC32&nbsp;数据手册IO部分）<br />Every&nbsp;I/O&nbsp;module&nbsp;register&nbsp;has&nbsp;a&nbsp;corresponding&nbsp;CLR<br />(clear),&nbsp;SET&nbsp;(set)&nbsp;and&nbsp;INV&nbsp;(invert)&nbsp;register&nbsp;designed&nbsp;to<br />provide&nbsp;fast&nbsp;atomic&nbsp;bit&nbsp;manipulations.&nbsp;As&nbsp;the&nbsp;name&nbsp;of<br />the&nbsp;register&nbsp;implies,&nbsp;a&nbsp;value&nbsp;written&nbsp;to&nbsp;a&nbsp;SET,&nbsp;CLR&nbsp;or<br />INV&nbsp;register&nbsp;effectively&nbsp;performs&nbsp;the&nbsp;implied&nbsp;operation,<br />but&nbsp;only&nbsp;on&nbsp;the&nbsp;corresponding&nbsp;base&nbsp;register&nbsp;and&nbsp;only<br />bits&nbsp;specified&nbsp;as&nbsp;‘1’&nbsp;are&nbsp;modified.&nbsp;Bits&nbsp;specified&nbsp;as&nbsp;‘0’<br />are&nbsp;not&nbsp;modified.<br />Reading&nbsp;SET,&nbsp;CLR&nbsp;and&nbsp;INV&nbsp;registers&nbsp;returns&nbsp;undefined<br />values.&nbsp;To&nbsp;see&nbsp;the&nbsp;affects&nbsp;of&nbsp;a&nbsp;write&nbsp;operation&nbsp;to&nbsp;a&nbsp;SET,<br />CLR&nbsp;or&nbsp;INV&nbsp;register,&nbsp;the&nbsp;base&nbsp;register&nbsp;must&nbsp;be&nbsp;read.<br />To&nbsp;set&nbsp;PORTC&nbsp;bit&nbsp;0,&nbsp;write&nbsp;to&nbsp;the&nbsp;LATSET&nbsp;register:<br />LATCSET&nbsp;=&nbsp;0x0001;<br />To&nbsp;clear&nbsp;PORTC&nbsp;bit&nbsp;0,&nbsp;write&nbsp;to&nbsp;the&nbsp;LATCLR&nbsp;register:<br />LATCCLR&nbsp;=&nbsp;0x0001;<br />To&nbsp;toggle&nbsp;PORTC&nbsp;bit&nbsp;0,&nbsp;write&nbsp;to&nbsp;the&nbsp;LATINV&nbsp;register:<br />LATCINV&nbsp;=&nbsp;0x0001;<br /><br />IO输出就是一条对相关IO寄存器的置位，清零，翻转别名寄存器的写操作，<br />而IO寄存器是接在SYSCLK总线上的。<br /><br />PIC32的IO当然远比CM3快。
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zyok 发表于 2009-1-9 09:24 | 显示全部楼层

两位真有兴致~呵呵

一个是PIC&nbsp;fans？一个是CM3&nbsp;fans?
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machunshui 发表于 2009-1-9 09:33 | 显示全部楼层

fans倒是不错，但是只要**说道理，又有何妨?

fans倒是不错，但是只要坚持说道理，又有何妨?
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machunshui 发表于 2009-1-9 10:07 | 显示全部楼层

清零指令

sw&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;$a0,&nbsp;0($s0)&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;/*&nbsp;clear&nbsp;specified&nbsp;bits&nbsp;*/<br /><br />看看是不是和2812相似呢？<br /><br />反正是远比CM3快
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machunshui 发表于 2009-1-9 10:18 | 显示全部楼层

比较

TMS320F2812:<br /><br />MOVW&nbsp;DP,#0x01BF<br />ORR&nbsp;@1,#0x2000<br /><br />PIC32:<br />la&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;$s0,&nbsp;LATACLR<br />sw&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;$a0,&nbsp;0($s0)&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;/*&nbsp;clear&nbsp;specified&nbsp;bits&nbsp;*/<br /><br />其实严格的说都不是一条指令，都包括一条取外设寄存器地址的指令，<br /><br />因为外设寄存器比较不是内核寄存器。<br /><br />当然如果连续操作，都是一条指令.<br /><br />应该都比CM3快不少。<br /><br />还有一点就是CM3的&nbsp;<br /><br />LDR&nbsp;R0,[xxxx]<br />STR&nbsp;R0,[xxxx]<br /><br />可能都不一定是一个时钟周期。<br /><br />PIC32的IO寄存器是接在SYSCLK上，确保了其对IO寄存器的操作是1个时钟周期<br />
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machunshui 发表于 2009-1-9 10:48 | 显示全部楼层

其实这还牵涉到IO模块是否接在SYSCLK总线上

其实这还牵涉到IO模块是否接在SYSCLK总线上。<br />不光是指令数目的问题。<br /><br />以NXP的LPC2000&nbsp;ARM7为例:<br /><br />如果&nbsp;用普通IO：<br />&nbsp;&nbsp;&nbsp;&nbsp;94:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;IOCLR&nbsp;|=&nbsp;SPI_595_LAT;&nbsp;<br />0x00000D20&nbsp;&nbsp;E59F2190&nbsp;&nbsp;LDR&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;R2,[PC,#0x0190]<br />0x00000D24&nbsp;&nbsp;E592200C&nbsp;&nbsp;LDR&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;R2,[R2,#0x000C]<br />0x00000D28&nbsp;&nbsp;E3822502&nbsp;&nbsp;ORR&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;R2,R2,#0x00800000<br />0x00000D2C&nbsp;&nbsp;E59F3184&nbsp;&nbsp;LDR&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;R3,[PC,#0x0184]<br />0x00000D30&nbsp;&nbsp;E583200C&nbsp;&nbsp;STR&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;R2,[R3,#0x000C]<br /><br />用快速FIO：<br />&nbsp;&nbsp;&nbsp;&nbsp;73:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;FIODIR&nbsp;|=&nbsp;SPIOUT;&nbsp;<br />0x00000DE4&nbsp;&nbsp;E59F039C&nbsp;&nbsp;LDR&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;R0,[PC,#0x039C]<br />0x00000DE8&nbsp;&nbsp;E5900000&nbsp;&nbsp;LDR&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;R0,[R0]<br />0x00000DEC&nbsp;&nbsp;E3800040&nbsp;&nbsp;ORR&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;R0,R0,#0x00000040<br />0x00000DF0&nbsp;&nbsp;E59F1390&nbsp;&nbsp;LDR&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;R1,[PC,#0x0390]<br />0x00000DF4&nbsp;&nbsp;E5810000&nbsp;&nbsp;STR&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;R0,[R1]<br /><br />指令数目一样，但是普通IO绝对不是5个指令周期,<br /><br />快速FIO，好像也只能提供最大17.5MHz的IO操作速度<br /><br />但是快速FIO提供了比普通IO好的多的速度,<br />因为快速FIO接在高速总线上的，<br />二者的速度差别很大。<br /><br />所以，确保IO模块都是接在SYSCLK总线上，数指令个数才有意义
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machunshui 发表于 2009-1-9 10:52 | 显示全部楼层

如果IO模块接在SYSCLK总线上，对IO的连续操作将是单周期

如果IO模块接在SYSCLK总线上，对IO的连续操作将是单周期，<br /><br />偶尔操作慢一点，<br /><br />这牵涉到取IO寄存器地址，以及取立即数。
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machunshui 发表于 2009-1-9 11:12 | 显示全部楼层

其实有人如果感兴趣，可以测一下

<br />方法：<br />1.设置好定时器，让定时器运行<br /><br />2.测试伪代码:<br /><br />temp1&nbsp;=&nbsp;Rtime；//&nbsp;设Rtime是定时器的计数寄存器<br />IO&nbsp;操作1；<br />IO&nbsp;操作2<br />temp2&nbsp;＝&nbsp;Rtime；<br /><br />if(temp2&nbsp;&gt&nbsp;temp1)<br />time&nbsp;＝&nbsp;temp2－temp1；<br />else<br />time&nbsp;=&nbsp;temp2&nbsp;+&nbsp;MAX_TIME&nbsp;-time1;//MAX_TIME定时计数器满值<br /><br />time值&nbsp;减去读取定时器的计数寄存器的两条指令的时钟数目就是IO操作的时钟数目。<br /><br />当然必须是实际硬件才可靠，软仿不一定。
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machunshui 发表于 2009-1-9 12:24 | 显示全部楼层

CM3的GPIO果然是桥接的，速度不会快

CM3的GPIO果然是桥接的，速度不会快
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machunshui 发表于 2009-1-9 12:39 | 显示全部楼层

看看PIC32，IO接在系统时钟总线，其他外设接在外设总线

看看PIC32，IO接在系统时钟总线，其他外设接在外设总线<br /><br />2812&nbsp;IO接在外设总线，CM3接在APB2总线，都不是接在系统时钟总线上，<br /><br />速度能一样吗？
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ijk 发表于 2009-1-9 14:07 | 显示全部楼层

CM3接在APB2总线

&nbsp;&nbsp;CM3接在APB2总线？谁说的？GPIO接在CM3的AHB总线上就不行吗？
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lanyong 发表于 2009-1-9 14:22 | 显示全部楼层

靠,看得我眼睛花

我8bit还没搞醒豁<br /><br />又来32bit的了。<br /><br />哎.整不归依.
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machunshui 发表于 2009-1-9 19:27 | 显示全部楼层

APB2是可以设置为SYSCLK同频

APB2是可以设置为SYSCLK同频,但这样将使链接到APB2总线上的其他外设的以高频工作,增加系统功耗.<br /><br />CM3的IO操作速度慢的还有一个原因就是LDA,STA指令周期,不是单周期,<br /><br />好像不是2周期,就是3周期.<br /><br />LDA&nbsp;R0,&nbsp;[PC,#0x0BC]<br />MOVS&nbsp;R1&nbsp;#0x1<br />STR&nbsp;R1,&nbsp;[R0,#0]<br /><br />可是比PIC32慢不少
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yan211 发表于 2009-1-14 13:19 | 显示全部楼层

被人设套了

争论半天&nbsp;被人搞陷阱了&nbsp;快了就好么<br />M4K支持每个中断有中断入口么&nbsp;，不然增多很多入口判断<br />另外就是编译效率&nbsp;看看PIC32的ucos移植&nbsp;比CORTEX的多出一倍不止<br />
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