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关于uart的单线半双工模式的配置

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UART, TE, AN, TI, ce
在飞思卡尔的uart_C1的看到"LOOPS"位
Loop Mode Select
When LOOPS is set, the RxD pin is disconnected from the UART and the transmitter output is internally
connected to the receiver input. The transmitter and the receiver must be enabled to use the loop function.
0 Normal operation.
1 Loop mode where transmitter output is internally connected to receiver input. The receiver input is
determined by RSRC.
即uart是支持单线模式的(备注:收发共用一个管脚)可以通过配置uart_C3中uart_C3_TXDIR_MASK来设置为是发送还是接收。
是有相关的demo可以提供参看。

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FSL_TICS_Jeremy| | 2015-2-15 09:36 | 只看该作者
你好,楼主!
没有单线半双工模式的的例程代码提供,你需要根据Singe-wire operation的特点,自己编写代码。


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板凳
LZR13179|  楼主 | 2015-4-8 19:21 | 只看该作者



void uart_single_init(UART_MemMapPtr uartch, int sysclk, int baud)
{

    register uint16 sbr, brfa;
    uint8 temp;
   
        /* Enable the clock to the selected UART */   
    if(uartch == UART0_BASE_PTR)
                SIM_SCGC4 |= SIM_SCGC4_UART0_MASK;
    else
            if (uartch == UART1_BASE_PTR)
                        SIM_SCGC4 |= SIM_SCGC4_UART1_MASK;
            else
                    if (uartch == UART2_BASE_PTR)
                            SIM_SCGC4 |= SIM_SCGC4_UART2_MASK;
                    else
                            if(uartch == UART3_BASE_PTR)
                                    SIM_SCGC4 |= SIM_SCGC4_UART3_MASK;
                            else
                                    if(uartch == UART4_BASE_PTR)
                                            SIM_SCGC1 |= SIM_SCGC1_UART4_MASK;
                                    else
                                            SIM_SCGC1 |= SIM_SCGC1_UART5_MASK;
    /* Make sure that the transmitter and receiver are disabled while we
     * change settings.
     */
    UART_C2_REG(uartch) &= ~(UART_C2_TE_MASK| UART_C2_RE_MASK );

    /* Configure the UART for 8-bit mode, no parity */
    UART_C1_REG(uartch) |= (UART_C1_LOOPS_MASK | UART_C1_RSRC_MASK);
    /* Calculate baud settings */
    sbr = (uint16)((sysclk*1000)/(baud * 16));
        
    /* Save off the current value of the UARTx_BDH except for the SBR field */
    temp = UART_BDH_REG(uartch) & ~(UART_BDH_SBR(0x1F));
   
    UART_BDH_REG(uartch) = temp |  UART_BDH_SBR(((sbr & 0x1F00) >> 8));
    UART_BDL_REG(uartch) = (uint8)(sbr & UART_BDL_SBR_MASK);
   
    /* Determine if a fractional divider is needed to get closer to the baud rate */
    brfa = (((sysclk*32000)/(baud * 16)) - (sbr * 32));
   
    /* Save off the current value of the UARTx_C4 register except for the BRFA field */
    temp = UART_C4_REG(uartch) & ~(UART_C4_BRFA(0x1F));
   
    UART_C4_REG(uartch) = temp |  UART_C4_BRFA(brfa);   

    /* Enable receiver and transmitter */
        UART_C2_REG(uartch) |= (UART_C2_TE_MASK| UART_C2_RE_MASK );

}


int uart_single_wire_test()
{
    UART_MemMapPtr module1, module2;
    char ch;
    int error = 0;

    printf("\n\nStarting setup for UART single wire mode tests.\n");

    /* Determine which UART to use as module1 for testing. UART2 or UART3
     * could be used. We'll use UART2 as long as it isn't used as the TERM_PORT.
     */

  
       module1 = UART1_BASE_PTR;   // set the module pointer

      printf("\nUsing UART1 on the daughter card as module1.\n");


    /* Determine which UART to use as module2 for testing. UART4 or UART5
     * could be used. We'll use UART4 as long as it isn't used as the TERM_PORT.
     */
         
       module2 = UART3_BASE_PTR;   // set the module pointer

    printf("\nUsing UART3 on the daughter card as module2.\n");
   
    printf("Setup complete. Starting UART single wire mode tests...\n");

   
    /* Configure both UARTs for single wire mode */
  //  UART_C1_REG(module1) |= (UART_C1_LOOPS_MASK | UART_C1_RSRC_MASK);
//   UART_C1_REG(module2) |= (UART_C1_LOOPS_MASK | UART_C1_RSRC_MASK);

    /* Test sending data from module1 to module2 */
   
    /* Configure the module1 TXD pin as an output */
    UART_C3_REG(module1) |= UART_C3_TXDIR_MASK;
        /*
        //²âÊÔ·¢ËÍ
        while(1)
        {
                uart_putchar(module1,0x01);
        }
        */
       
        /*
        //²âÊÔʹÓÃ:PC·¢Ë͸øUART3,uart3½«½ÓÊÕµÄÊý¾Ýͨ¹ýuart1»áËÍPC
        while(1)
        {
                  ch = uart_getchar(module2);
                   uart_putchar(module1,ch );
       
        }
        */
    uart_putchar(module1,0x01);

    /* Get the received data from module2 */
    ch = uart_getchar(module2);
   
    /* Test to make sure the data matches */
    if( ch != 0x01)
    {
        error++;
        printf("\nERR! Incorrect data received. Expected: 0xAA Recieved: 0x%02X", ch);
    }
   
    /* Make sure that module1 ignored the data (since it sent it) */
    if( uart_getchar_present(module1) )
    {
        error++;
        printf("\nERR! Data received on module1 when only module2 should have received.");
    }
      

    /* Test sending data from module2 to module1 */
   
    /* Configure the module1 TXD pin as an input */
    UART_C3_REG(module1) &= ~UART_C3_TXDIR_MASK;
   
    /* Configure the module2 TXD pin as an output */
    UART_C3_REG(module2) |= UART_C3_TXDIR_MASK;   
   
    uart_putchar(module2,0x55);
   
    /* Get the received data from module1 */
    ch = uart_getchar(module1);
   
    /* Test to make sure the data matches */
    if( ch != 0x55)
    {
        error++;
        printf("\nERR! Incorrect data received. Expected: 0x55 Recieved: 0x%02X", ch);
    }
   
    /* Make sure that module2 ignored the data (since it sent it) */
    if( uart_getchar_present(module2) )
    {
        error++;
        printf("\nERR! Data received on module2 when only module1 should have received.");
    }
   

    /* Clear TXDIR for both UARTs */
    UART_C3_REG(module1) &= ~UART_C3_TXDIR_MASK;
    UART_C3_REG(module2) &= ~UART_C3_TXDIR_MASK;

    /* Disable single wire mode for both UARTs*/
//   UART_C1_REG(module1) &= ~(UART_C1_LOOPS_MASK | UART_C1_RSRC_MASK);
  //  UART_C1_REG(module2) &= ~(UART_C1_LOOPS_MASK | UART_C1_RSRC_MASK);
    printf(" -------------------------endUART single wire mode tests-------------------------\n");



    return error;   
}     

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mazxcv| | 2017-8-29 16:25 | 只看该作者
sdsacsdfsfcsav

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