|
compiler: keil arm<br />cpu: lpc2378<br />在startup.s<br />;/*****************************************************************************<br />;* startup.s: startup file for NXP LPC230x Family Microprocessors<br />;*<br />;* Copyright(C) 2006, NXP Semiconductor<br />;* All rights reserved.<br />;*<br />;* History<br />;* 2006.09.01 ver 1.00 Prelimnary version, first Release<br />;*<br />;*****************************************************************************/<br /> PRESERVE8<br /><br />;/*<br />; * The STARTUP.S code is executed after CPU Reset. This file may be <br />; * translated with the following SET symbols. In uVision these SET <br />; * symbols are entered under Options - ASM - Define.<br />; *<br />; * REMAP: when set the startup code initializes the register MEMMAP <br />; * which overwrites the settings of the CPU configuration pins. The <br />; * startup and interrupt vectors are remapped from:<br />; * 0x00000000 default setting (not remapped)<br />; * 0x40000000 when RAM_MODE is used<br />; *<br />; * RAM_MODE: when set the device is configured for code execution<br />; * from on-chip RAM starting at address 0x40000000. <br />; */<br /><br /><br />; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs<br /><br />Mode_USR EQU 0x10<br />Mode_FIQ EQU 0x11<br />Mode_IRQ EQU 0x12<br />Mode_SVC EQU 0x13<br />Mode_ABT EQU 0x17<br />Mode_UND EQU 0x1B<br />Mode_SYS EQU 0x1F<br /><br />I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled<br />F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled<br /><br /><br />;// <h> Stack Configuration (Stack Sizes in Bytes)<br />;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8><br />;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8><br />;// <o2> Abort Mode <0x0-0xFFFFFFFF:8><br />;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8><br />;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8><br />;// <o5> User/System Mode <0x0-0xFFFFFFFF:8><br />;// </h><br /><br />UND_Stack_Size EQU 0x00000004<br />SVC_Stack_Size EQU 0x00000100<br />ABT_Stack_Size EQU 0x00000004<br />FIQ_Stack_Size EQU 0x00000004<br />IRQ_Stack_Size EQU 0x00000100<br />USR_Stack_Size EQU 0x00001000;modify by sliu<br /><br />Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size + USR_Stack_Size)<br /><br /> AREA STACK, NOINIT, READWRITE, ALIGN=3<br />Stack_Mem SPACE Stack_Size<br /><br />Stack_Top EQU Stack_Mem + Stack_Size<br /><br /><br />;// <h> Heap Configuration<br />;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF><br />;// </h><br /><br />Heap_Size EQU 0x00002240<br /><br /> AREA HEAP, NOINIT, READWRITE, ALIGN=3<br />Heap_Mem SPACE Heap_Size<br /><br />; Area Definition and Entry Point<br />; Startup Code must be linked first at Address at which it expects to run.<br /><br /> AREA RESET, CODE, READONLY<br /> ARM<br /><br />; Exception Vectors<br />; Mapped to Address 0.<br />; Absolute addressing mode must be used.<br />; Dummy Handlers are implemented as infinite loops which can be modified.<br /><br />Vectors LDR PC, Reset_Addr <br /> LDR PC, Undef_Addr<br /> LDR PC, SWI_Addr<br /> LDR PC, PAbt_Addr<br /> LDR PC, DAbt_Addr<br /> NOP ; Reserved Vector <br />; LDR PC, IRQ_Addr<br /> LDR PC, [PC, #-0x0120] ; Vector from VicVectAddr<br /> LDR PC, FIQ_Addr<br /><br />Reset_Addr DCD Reset_Handler<br />Undef_Addr DCD Undef_Handler<br />SWI_Addr DCD SWI_Handler<br />PAbt_Addr DCD PAbt_Handler<br />DAbt_Addr DCD DAbt_Handler<br /> DCD 0xB9206E28 ; Reserved Address <br />IRQ_Addr DCD IRQ_Handler<br />FIQ_Addr DCD FIQ_Handler<br /><br />Undef_Handler B Undef_Handler<br />SWI_Handler B SWI_Handler<br />PAbt_Handler B PAbt_Handler<br />DAbt_Handler B DAbt_Handler<br />IRQ_Handler B IRQ_Handler<br />FIQ_Handler B FIQ_Handler<br /><br /><br />; Reset Handler<br /><br /> EXPORT Reset_Handler<br />Reset_Handler <br /><br />; Setup Stack for each mode<br /> LDR R0, =Stack_Top<br /><br />; Enter Undefined Instruction Mode and set its Stack Pointer<br /> MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit<br /> MOV SP, R0<br /> SUB R0, R0, #UND_Stack_Size<br /><br />; Enter Abort Mode and set its Stack Pointer<br /> MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit<br /> MOV SP, R0<br /> SUB R0, R0, #ABT_Stack_Size<br /><br />; Enter FIQ Mode and set its Stack Pointer<br /> MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit<br /> MOV SP, R0<br /> SUB R0, R0, #FIQ_Stack_Size<br /><br />; Enter IRQ Mode and set its Stack Pointer<br /> MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit<br /> MOV SP, R0<br /> SUB R0, R0, #IRQ_Stack_Size<br /><br />; Enter Supervisor Mode and set its Stack Pointer<br /> MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit<br /> MOV SP, R0<br /> SUB R0, R0, #SVC_Stack_Size<br /><br />; Enter User Mode and set its Stack Pointer<br /> MSR CPSR_c, #Mode_USR<br /> MOV SP, R0<br /> SUB SL, SP, #USR_Stack_Size<br /> <br /> ;BL __user_initial_stackheap<br /> IMPORT TargetResetInit<br /> BL TargetResetInit<br /><br />; Enter the C code<br /><br /> IMPORT __main<br /> LDR R0, =__main<br /> BX R0<br /><br /><br />; User Initial Stack & Heap<br /> AREA |.text|, CODE, READONLY<br /><br /> IMPORT __use_two_region_memory<br /> EXPORT __user_initial_stackheap<br />__user_initial_stackheap<br /><br /> LDR R0, = Heap_Mem<br /> LDR R1, =(Stack_Mem + USR_Stack_Size)<br /> LDR R2, = (Heap_Mem + Heap_Size)<br /> LDR R3, = Stack_Mem<br /> BX LR<br /><br /> END<br />我已经给了heapsize.<br />谢谢！ |
|
楼主
