跑一下SAM4N例程(二十四)：SS1306

#ifndef CONF_BOARD_H_INCLUDED

#define CONF_BOARD_H_INCLUDED



/** Enable the OLED screen. */

#define CONF_BOARD_SPI

#define CONF_BOARD_SPI_NPCS2



#define CONF_BOARD_OLED_UG_2832HSWEG04



#endif /* CONF_BOARD_H_INCLUDED */

#ifndef CONF_CLOCK_H_INCLUDED

#define CONF_CLOCK_H_INCLUDED



// ===== System Clock (MCK) Source Options

//#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_SLCK_RC

//#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_SLCK_XTAL

//#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_SLCK_BYPASS

//#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_MAINCK_4M_RC

//#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_MAINCK_8M_RC

//#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_MAINCK_12M_RC

//#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_MAINCK_XTAL

//#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_MAINCK_BYPASS

#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_PLLACK



// ===== System Clock (MCK) Prescaler Options   (Fmck = Fsys / (SYSCLK_PRES))

//#define CONFIG_SYSCLK_PRES          SYSCLK_PRES_1

#define CONFIG_SYSCLK_PRES          SYSCLK_PRES_2

//#define CONFIG_SYSCLK_PRES          SYSCLK_PRES_4

//#define CONFIG_SYSCLK_PRES          SYSCLK_PRES_8

//#define CONFIG_SYSCLK_PRES          SYSCLK_PRES_16

//#define CONFIG_SYSCLK_PRES          SYSCLK_PRES_32

//#define CONFIG_SYSCLK_PRES          SYSCLK_PRES_64

//#define CONFIG_SYSCLK_PRES          SYSCLK_PRES_3



// ===== PLL0 (A) Options   (Fpll = (Fclk * PLL_mul) / PLL_div)

// Use mul and div effective values here.

#define CONFIG_PLL0_SOURCE          PLL_SRC_MAINCK_8M_RC

#define CONFIG_PLL0_MUL             25

#define CONFIG_PLL0_DIV             1



// ===== Target frequency (System clock)

// - Internal RC frequency: 8MHz

// - System clock source: PLLA

// - System clock prescaler: 2 (divided by 2)

// - PLLA source: 8M_RC

// - PLLA output: 8M_RC * 25 / 1

// - System clock: 8M_RC * 25 / 1 / 2 = 100MHz



#endif /* CONF_CLOCK_H_INCLUDED */

/* Possibility to change low-level configurations here. */



//! Default Configuration of SPI Master Delay BCS

#define CONFIG_SPI_MASTER_DELAY_BCS            0x00



//! Default Configuration of SPI Master Bits per Transfer Definition

#define CONFIG_SPI_MASTER_BITS_PER_TRANSFER    8



//! Default Configuration of SPI Master Delay BCT

#define CONFIG_SPI_MASTER_DELAY_BCT            0x00



//! Default Configuration of SPI Master Delay BS

#define CONFIG_SPI_MASTER_DELAY_BS             0x00



//! Default Configuration of SPI Master Dummy Field

// #define CONFIG_SPI_MASTER_DUMMY                0xFF



#endif /* CONF_SPI_MASTER_H_INCLUDED */

#ifndef CONF_SSD1306_H_INCLUDED

#define CONF_SSD1306_H_INCLUDED



// Interface configuration for SAM4N Xplained Pro

#define SSD1306_SPI_INTERFACE

#define SSD1306_SPI SPI



#define SSD1306_DC_PIN       UG_2832HSWEG04_DATA_CMD_GPIO

#define SSD1306_RES_PIN      UG_2832HSWEG04_RESET_GPIO

#define SSD1306_CS_PIN       UG_2832HSWEG04_SS



// Minimum clock period is 50ns[url=home.php?mod=space&uid=517595]@3.3V[/url] -> max frequency is 20MHz

#define SSD1306_CLOCK_SPEED          UG_2832HSWEG04_BAUDRATE

#define SSD1306_DISPLAY_CONTRAST_MAX 40

#define SSD1306_DISPLAY_CONTRAST_MIN 30

// fill display with lines

        for (page_address = 0; page_address <= 7; page_address++) {

                ssd1306_set_page_address(page_address);

                for (column_address = 0; column_address < 128; column_address++) {

                        ssd1306_set_column_address(column_address);

                        /* fill every other pixel in the display. This will produce

                        horizontal lines on the display. */

                        ssd1306_write_data(0x6F);

                }

        }



        // scroll the display using hardware support in the LCD controller

        while (true) {

                ssd1306_set_display_start_line_address(start_line_address++);

                delay_ms(250);

        }