PRESERVE8
; Area Definition and Entry Point
; Startup Code must be linked first at Address at which it expects to run.
AREA RESET, CODE, READONLY
ARM
; Exception Vectors
; Mapped to Address 0.
; Absolute addressing mode must be used.
; Dummy Handlers are implemented as infinite loops which can be modified.
Vectors LDR PC, Reset_Addr
LDR PC, Undef_Addr
LDR PC, SWI_Addr
LDR PC, PAbt_Addr
LDR PC, DAbt_Addr
NOP ; Reserved Vector
LDR PC, IRQ_Addr
LDR PC, FIQ_Addr
IF IntVT_SETUP <> 0
;Interrupt Vector Table Address
HandleEINT0 EQU IntVTAddress
HandleEINT1 EQU IntVTAddress +4
HandleEINT2 EQU IntVTAddress +4*2
HandleEINT3 EQU IntVTAddress +4*3
HandleEINT4_7 EQU IntVTAddress +4*4
HandleEINT8_23 EQU IntVTAddress +4*5
HandleCAM EQU IntVTAddress +4*6
HandleBATFLT EQU IntVTAddress +4*7
HandleTICK EQU IntVTAddress +4*8
HandleWDT EQU IntVTAddress +4*9
HandleTIMER0 EQU IntVTAddress +4*10
HandleTIMER1 EQU IntVTAddress +4*11
HandleTIMER2 EQU IntVTAddress +4*12
HandleTIMER3 EQU IntVTAddress +4*13
HandleTIMER4 EQU IntVTAddress +4*14
HandleUART2 EQU IntVTAddress +4*15
HandleLCD EQU IntVTAddress +4*16
HandleDMA0 EQU IntVTAddress +4*17
HandleDMA1 EQU IntVTAddress +4*18
HandleDMA2 EQU IntVTAddress +4*19
HandleDMA3 EQU IntVTAddress +4*20
HandleMMC EQU IntVTAddress +4*21
HandleSPI0 EQU IntVTAddress +4*22
HandleUART1 EQU IntVTAddress +4*23
HandleNFCON EQU IntVTAddress +4*24
HandleUSBD EQU IntVTAddress +4*25
HandleUSBH EQU IntVTAddress +4*26
HandleIIC EQU IntVTAddress +4*27
HandleUART0 EQU IntVTAddress +4*28
HandleSPI1 EQU IntVTAddress +4*39
HandleRTC EQU IntVTAddress +4*30
HandleADC EQU IntVTAddress +4*31
IRQ_Entry
sub sp,sp,#4 ;reserved for PC
stmfd sp!,{r8-r9}
ldr r9,=INTOFFSET
ldr r9,[r9]
ldr r8,=HandleEINT0
add r8,r8,r9,lsl #2
ldr r8,[r8]
str r8,[sp,#8]
ldmfd sp!,{r8-r9,pc}
ENDIF
Reset_Addr DCD Reset_Handler
Undef_Addr DCD Undef_Handler
SWI_Addr DCD SWI_Handler
PAbt_Addr DCD PAbt_Handler
DAbt_Addr DCD DAbt_Handler
DCD 0 ; Reserved Address
IRQ_Addr DCD IRQ_Handler
FIQ_Addr DCD FIQ_Handler
Undef_Handler B Undef_Handler
SWI_Handler B SWI_Handler
PAbt_Handler B PAbt_Handler
DAbt_Handler B DAbt_Handler
IF IntVT_SETUP <> 1
IRQ_Handler B IRQ_Handler
ENDIF
IF IntVT_SETUP <> 0
IRQ_Handler B IRQ_Entry
ENDIF
FIQ_Handler B FIQ_Handler
; Memory Controller Configuration
IF MC_SETUP <> 0
MC_CFG
DCD BWSCON_Val
DCD BANKCON0_Val
DCD BANKCON1_Val
DCD BANKCON2_Val
DCD BANKCON3_Val
DCD BANKCON4_Val
DCD BANKCON5_Val
DCD BANKCON6_Val
DCD BANKCON7_Val
DCD REFRESH_Val
DCD BANKSIZE_Val
DCD MRSRB6_Val
DCD MRSRB7_Val
ENDIF
; Clock Management Configuration
IF CLOCK_SETUP <> 0
CLK_CFG
DCD LOCKTIME_Val
DCD CLKDIVN_Val
DCD UPLLCON_Val
DCD MPLLCON_Val
DCD CLKSLOW_Val
DCD CLKCON_Val
DCD CAMDIVN_Val
ENDIF
; I/O Configuration
IF PIO_SETUP <> 0
PIOA_CFG
DCD PCONA_Val
PIOB_CFG DCD PCONB_Val
DCD PUPB_Val
PIOC_CFG DCD PCONC_Val
DCD PUPC_Val
PIOD_CFG DCD PCOND_Val
DCD PUPD_Val
PIOE_CFG DCD PCONE_Val
DCD PUPE_Val
PIOF_CFG DCD PCONF_Val
DCD PUPF_Val
PIOG_CFG DCD PCONG_Val
DCD PUPG_Val
PIOH_CFG DCD PCONH_Val
DCD PUPH_Val
PIOJ_CFG DCD PCONJ_Val
DCD PUPJ_Val
ENDIF
; Reset Handler
EXPORT Reset_Handler
Reset_Handler
IF WT_SETUP <> 0
LDR R0, =WT_BASE
LDR R1, =WTCON_Val
LDR R2, =WTDAT_Val
STR R2, [R0, #WTCNT_OFS]
STR R2, [R0, #WTDAT_OFS]
STR R1, [R0, #WTCON_OFS]
ENDIF
IF CLOCK_SETUP <> 0
LDR R0, =CLK_BASE
ADR R8, CLK_CFG
LDMIA R8, {R1-R7}
STR R1, [R0, #LOCKTIME_OFS]
STR R2, [R0, #CLKDIVN_OFS]
STR R3, [R0, #UPLLCON_OFS]
nop
nop
nop
nop
nop
nop
nop
STR R4, [R0, #MPLLCON_OFS]
STR R5, [R0, #CLKSLOW_OFS]
STR R6, [R0, #CLKCON_OFS]
STR R7, [R0, #CAMDIVN_OFS]
ENDIF
IF MC_SETUP <> 0
ADR R13, MC_CFG
LDMIA R13, {R0-R12}
LDR R13, =MC_BASE
STMIA R13, {R0-R12}
ENDIF
IF PIO_SETUP <> 0
LDR R13, =PIO_BASE
IF PIOA_SETUP <> 0
ADR R0, PIOA_CFG
STR R0, [R13, #PCONA_OFS]
ENDIF
IF PIOB_SETUP <> 0
ADR R0, PIOB_CFG
LDR R1, [R0,#4]
STR R0, [R13, #PCONB_OFS]
STR R1, [R13, #PUPB_OFS]
ENDIF
IF PIOC_SETUP <> 0
ADR R0, PIOC_CFG
LDR R1, [R0,#4]
STR R0, [R13, #PCONC_OFS]
STR R1, [R13, #PUPC_OFS]
ENDIF
IF PIOD_SETUP <> 0
ADR R0, PIOD_CFG
LDR R1, [R0,#4]
STR R0, [R13, #PCOND_OFS]
STR R1, [R13, #PUPD_OFS]
ENDIF
IF PIOE_SETUP <> 0
ADR R0, PIOE_CFG
LDR R1, [R0,#4]
STR R0, [R13, #PCONE_OFS]
STR R1, [R13, #PUPE_OFS]
ENDIF
IF PIOF_SETUP <> 0
ADR R0, PIOF_CFG
LDR R1, [R0,#4]
STR R0, [R13, #PCONF_OFS]
STR R1, [R13, #PUPF_OFS]
ENDIF
IF PIOG_SETUP <> 0
ADR R0, PIOG_CFG
LDR R1, [R0,#4]
STR R0, [R13, #PCONG_OFS]
STR R1, [R13, #PUPG_OFS]
ENDIF
IF PIOH_SETUP <> 0
ADR R0, PIOH_CFG
LDR R1, [R0,#4]
STR R0, [R13, #PCONH_OFS]
STR R1, [R13, #PUPH_OFS]
ENDIF
IF PIOJ_SETUP <> 0
ADR R0, PIOJ_CFG
LDR R1, [R0,#4]
STR R0, [R13, #PCONJ_OFS]
STR R1, [R13, #PUPJ_OFS]
ENDIF
ENDIF
; Setup Stack for each mode
LDR R0, =Stack_Top
; Enter Undefined Instruction Mode and set its Stack Pointer
MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #UND_Stack_Size
; Enter Abort Mode and set its Stack Pointer
MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #ABT_Stack_Size
; Enter FIQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #FIQ_Stack_Size
; Enter IRQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #IRQ_Stack_Size
; Enter Supervisor Mode and set its Stack Pointer
MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #SVC_Stack_Size
; IMPORT MMU_EnableICache
; bl MMU_EnableICache
; Enter User Mode and set its Stack Pointer
MSR CPSR_c, #Mode_USR
MOV SP, R0
SUB SL, SP, #USR_Stack_Size
; Enter the C code
;
IMPORT __main
LDR R0, =__main
BX R0
; User Initial Stack & Heap
AREA |.text|, CODE, READONLY
; IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + USR_Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
END |
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