LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--模块功能:在曼彻斯特信号的上升沿产生时钟同步脉冲(近似的,模拟的,不是真正的脉冲)
Entity ER IS
PORT
(
R : OUT STD_LOGIC;
MANIN : IN STD_LOGIC;
CLK : IN STD_LOGIC --曼彻斯特输入信号
);
END ENTITY ER;
ARCHITECTURE ONE OF ER IS
SIGNAL MI : STD_LOGIC;
BEGIN
PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK = '1' THEN
IF MANIN = '1' OR MANIN = '0' THEN
MI <= MANIN;
R <= MI XOR MANIN;
END IF;
END IF;
END PROCESS;
END ONE; |