ECanaRegs.CANGIF0.all = 0xFFFFFFFF; /* Clear all interrupt flag bits */
ECanaRegs.CANGIF1.all = 0xFFFFFFFF;
/* Configure bit timing parameters for eCANA*/
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
// ECanaShadow.CANES.all = ECanaRegs.CANES.all;
do
{
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
} while(ECanaShadow.CANES.bit.CCE != 1 ); // Wait for CCE bit to be set..
ECanaShadow.CANBTC.all = 0;
//#if (CPU_FRQ_150MHZ) // CPU_FRQ_150MHz is defined in DSP2833x_Examples.h
/* The following block for all 150 MHz SYSCLKOUT (75 MHz CAN clock) - default. Bit rate = 1 Mbps
See Note at End of File */
ECanaShadow.CANBTC.bit.BRPREG = 9;
ECanaShadow.CANBTC.bit.TSEG2REG = 2;
ECanaShadow.CANBTC.bit.TSEG1REG = 10;
// ECanaShadow.CANBTC.bit.BRPREG =14 ;
// ECanaShadow.CANBTC.bit.TSEG2REG = 5;
// ECanaShadow.CANBTC.bit.TSEG1REG = 12;
// #endif
// #if (CPU_FRQ_100MHZ) // CPU_FRQ_100MHz is defined in DSP2833x_Examples.h
/* The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock). Bit rate = 1 Mbps
See Note at End of File */
// ECanaShadow.CANBTC.bit.BRPREG = 4;
// ECanaShadow.CANBTC.bit.TSEG2REG = 1;
// ECanaShadow.CANBTC.bit.TSEG1REG = 6;
// #endif