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各位朋友，帮忙看下下面的程序，看看那里需要修改，<br />报错提示如下：<br />Error (10818): Netlist error at JT.vhd(35): can't infer register for N[0] because it does not hold its value outside the clock edge<br />Error (10818): Netlist error at JT.vhd(35): can't infer register for N[1] because it does not hold its value outside the clock edge<br />Error (10818): Netlist error at JT.vhd(35): can't infer register for N[2] because it does not hold its value outside the clock edge<br />Error (10818): Netlist error at JT.vhd(35): can't infer register for N[3] because it does not hold its value outside the clock edge<br />Error (10818): Netlist error at JT.vhd(35): can't infer register for N[4] because it does not hold its value outside the clock edge<br />Error (10818): Netlist error at JT.vhd(35): can't infer register for N[5] because it does not hold its value outside the clock edge<br />Error (10818): Netlist error at JT.vhd(35): can't infer register for N[6] because it does not hold its value outside the clock edge<br />Error (10818): Netlist error at JT.vhd(35): can't infer register for M[0] because it does not hold its value outside the clock edge<br />Error (10818): Netlist error at JT.vhd(35): can't infer register for M[1] because it does not hold its value outside the clock edge<br />Error (10818): Netlist error at JT.vhd(35): can't infer register for M[2] because it does not hold its value outside the clock edge<br />Error (10818): Netlist error at JT.vhd(35): can't infer register for M[3] because it does not hold its value outside the clock edge<br />Error (10818): Netlist error at JT.vhd(35): can't infer register for M[4] because it does not hold its value outside the clock edge<br />Error (10818): Netlist error at JT.vhd(35): can't infer register for M[5] because it does not hold its value outside the clock edge<br />Error (10818): Netlist error at JT.vhd(35): can't infer register for M[6] because it does not hold its value outside the clock edge<br />Error (10822): HDL error at JT.vhd(35): couldn't implement registers for assignments on this clock edge<br />Error: Can't elaborate top-level user hierarchy<br />Error: Quartus II Analysis & Synthesis was unsuccessful. 16 errors, 8 warnings<br /> Info: Allocated 132 megabytes of memory during processing<br /> Error: Processing ended: Wed Jan 02 15:20:35 2008<br /> Error: Elapsed time: 00:00:02<br />Error: Quartus II Full Compilation was unsuccessful. 16 errors, 8 warnings<br /> 程序如下：<br />LIBRARY IEEE;<br />USE IEEE.STD_LOGIC_1164.ALL;<br />USE IEEE.STD_LOGIC_UNSIGNED.ALL;<br />ENTITY JT IS<br />PORT (CLK1: IN STD_LOGIC; <br /> RST : IN STD_LOGIC; <br /> JJ : IN STD_LOGIC;<br /> EW : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);<br /> SN : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);<br /> T1 : IN INTEGER RANGE 0 TO 99;<br /> T2 : IN INTEGER RANGE 0 TO 99;<br /> T3 : IN INTEGER RANGE 0 TO 99;<br /> Q1 : BUFFER INTEGER RANGE 0 TO 99;<br /> Q2 : BUFFER INTEGER RANGE 0 TO 99 );<br /><br />END ;<br />ARCHITECTURE kz OF JT IS<br />TYPE STATES IS (ST0,ST1,ST2,ST3);<br /> SIGNAL current_state,next_state:states := st0 ;<br /> SIGNAL M: INTEGER RANGE 0 TO 99 :=0;<br /> SIGNAL N: INTEGER RANGE 0 TO 99 :=0;<br /> BEGIN<br /> COM: PROCESS(T1,T2,T3,CURRENT_STATE,RST,CLK1)<br /> BEGIN <br /> IF RST = '1' THEN NEXT_STATE <= ST0;<br /> IF JJ = '1' THEN CURRENT_STATE<=CURRENT_STATE;M<=M;N<=N;<br /> ELSE<br /> CASE CURRENT_STATE IS<br /> WHEN ST0 => EW <= "010";SN <= "100";M <= T1;N<=T2; NEXT_STATE <= ST1;<br /> WHEN ST1 => EW <="001" ;SN <= "100";M <=T3;NEXT_STATE <= ST2;<br /> WHEN ST2 => EW <="100" ;SN <= "010";M <=T2;N<=T1; NEXT_STATE <= ST3;<br /> WHEN ST3 => EW <="100" ;SN <= "001";M <=T3; NEXT_STATE <= ST0;<br /> END CASE;<br /> END IF;END IF;<br /> IF ( CLK1'EVENT AND CLK1='1') THEN M <=M-1;N <=N-1;END IF;<br /> END PROCESS COM;<br /> REG: PROCESS (JJ,CLK1,M,N)<br /> BEGIN <br /> Q1 <= M;Q2 <= N;<br /> <br /> IF (M ="0" OR N ="0") THEN CURRENT_STATE <= NEXT_STATE;<br /> END IF; <br /> END PROCESS REG;<br /> END; |
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