我是个CPLD的新手，用maxplus写了一个计数器小程序。代码如下：<br />Timertest.vhd<br />library ieee;<br />use ieee.std_logic_1164.all;<br /><br />ENTITY TimerTest IS<br /> PORT(<br /> Reset : in std_logic;<br /> Clk : in std_logic;<br /> nWR : in std_logic;<br /> Data : in std_logic_vector(7 downto 0);<br /> Tout : out std_logic<br /> );<br />END TimerTest ;<br />ARCHITECTURE a OF TimerTest IS<br /> signal TSet: std_logic_vector(7 downto 0);<br /> signal EnClk: std_logic;<br /> COMPONENT TimerSet<br /> PORT(<br /> Reset : in std_logic;<br /> Data : in std_logic_vector(7 downto 0);<br /> nWR : in std_logic;<br /> EnClk : out std_logic<br /> );<br /> END COMPONENT;<br /> <br /> COMPONENT Timer<br /> port(<br /> Reset : in std_logic;<br /> Clk : in std_logic;<br /> Tout : out std_logic;<br /> EnClk : in std_logic<br /> );<br /> end component;<br />begin<br /> myTimer :Timer<br /> port map (<br /> Reset => Reset,<br /> Clk => Clk,<br /> Tout => Tout,<br /> EnClk => EnClk,<br /> );<br /> myTimerSet: TimerSet<br /> port map(<br /> Reset => Reset,<br /> Data => Data,<br /> nWR => nWR,<br /> EnClk => EnClk, <br /> );<br />END a;<br /><br />Timer.vhd<br /><br />library ieee;<br />use ieee.std_logic_1164.all;<br />use ieee.std_logic_unsigned.all;<br /><br />ENTITY Timer IS<br /> port(<br /> Reset : in std_logic;<br /> Clk : in std_logic;<br /> Tout : out std_logic;<br /> EnClk : in std_logic<br /> );<br />END Timer;<br /><br />ARCHITECTURE a OF Timer IS<br />signal TCounter :std_logic_vector(7 downto 0);<br />signal TT :std_logic;<br />BEGIN<br /> Tout<=TT;<br /> process(Clk)<br /> begin<br /> if(Reset='0') then<br /> TCounter<=X"1f";<br /> TT<='1';<br /> elsif rising_edge(Clk) then<br /> if(EnClk='1') then<br /> if(TCounter=X"00") then<br /> TCounter <=X"1f";<br /> TT <= not TT;<br /> else<br /> TCounter <= TCounter - 1;<br /> end if;<br /> end if;<br /> end if;<br /> end process;<br />END a;<br /><br /><br />TimerSet.vhd<br /><br />library ieee;<br />use ieee.std_logic_1164.all;<br />use ieee.std_logic_unsigned.all;<br /><br />ENTITY TimerSet IS<br /> PORT(<br /> Reset : in std_logic;<br /> Data : in std_logic_vector(7 downto 0);<br /> nWR : in std_logic;<br /> EnClk : out std_logic<br /> );<br />END TimerSet;<br /><br />ARCHITECTURE a OF TimerSet IS<br />BEGIN<br /> process(Reset,nWR,Data)<br /> begin<br /> if(Reset='0')then<br /> EnClk <='0';<br /> elsif(nWR='0') then<br /> EnClk <='1';<br /> end if;<br /> end process;<br />END a;<br /><br />仿真的结果Tout是正确的。<br />可是察看 TCounter 的值变化是不规律的。<br /><br />请各位高人 给与指点。 谢谢！ |
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