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现在在调fpga控制dds的程序，wclk，8位data，freq_ud的时序都没问题，但就是出不来波形，请高手指点<br />程序如下<br />--0x40000000<br />library ieee;<br />use ieee.std_logic_1164.all;<br />use ieee.std_logic_unsigned.all;<br /><br />entity dds_source is<br /> port(clk :in std_logic;<br /> fpga_reset :in std_logic;<br /> B_dir :out std_logic_vector(7 downto 0);<br /> B_oe :out std_logic_vector(7 downto 0);<br /> data :out std_logic_vector(7 downto 0);<br /> wclk :out std_logic;<br /> dds_reset :out std_logic;<br /> freq_ud :out std_logic<br /> );<br />end dds_source;<br /><br />architecture behavior of dds_source is<br />signal clkdiv :std_logic:='1';<br />begin<br /> B_dir <= "00000000";<br /> B_oe <= "00000000";<br /> <br /> process(clk)<br /> variable clkcnt :std_logic_vector(7 downto 0);<br /> begin<br /> if clk'event and clk='1' then<br /> if clkcnt="00000001" then<br /> clkcnt := (others=>'0');<br /> clkdiv <= not clkdiv;<br /> else<br /> clkcnt := clkcnt+1;<br /> end if;<br /> end if;<br /> end process;<br /> <br /> process(clkdiv)<br /> variable count :integer range 0 to 15;<br /> variable cnt :integer range 0 to 5;<br /> begin<br /> if fpga_reset='0' then<br /> wclk <= '0';<br /> freq_ud <= '0';<br /> count := 0;<br /> cnt := 0;<br /> elsif clkdiv'event and clkdiv='0' then<br /> case count is<br /> when 0 =><br /> data <= "00000000";<br /> if cnt=2 then<br /> wclk <= '1';<br /> cnt := cnt+1;<br /> elsif cnt=4 then<br /> wclk <= '0';<br /> cnt := cnt+1;<br /> elsif cnt=5 then<br /> count := 1;<br /> cnt := 0;<br /> else<br /> cnt := cnt+1;<br /> end if;<br /> when 1 =><br /> data <= "01000000";<br /> if cnt=2 then<br /> wclk <= '1';<br /> cnt := cnt+1;<br /> elsif cnt=4 then<br /> wclk <= '0';<br /> cnt := cnt+1;<br /> elsif cnt=5 then<br /> count := 2;<br /> cnt := 0;<br /> else<br /> cnt := cnt+1;<br /> end if;<br /> when 2 =><br /> data <= "00100000";<br /> if cnt=2 then<br /> wclk <= '1';<br /> cnt := cnt+1;<br /> elsif cnt=4 then<br /> wclk <= '0';<br /> cnt := cnt+1;<br /> elsif cnt=5 then<br /> count := 3;<br /> cnt := 0;<br /> else<br /> cnt := cnt+1;<br /> end if;<br /> when 3 =><br /> data <= "00010000";<br /> if cnt=2 then<br /> wclk <= '1';<br /> cnt := cnt+1;<br /> elsif cnt=4 then<br /> wclk <= '0';<br /> cnt := cnt+1;<br /> elsif cnt=5 then<br /> count := 4;<br /> cnt := 0;<br /> else<br /> cnt := cnt+1;<br /> end if;<br /><br /> when 4 =><br /> data <= "00001000";<br /> if cnt=2 then<br /> wclk <= '1';<br /> cnt := cnt+1;<br /> elsif cnt=4 then<br /> wclk <= '0';<br /> cnt := cnt+1;<br /> elsif cnt=5 then<br /> count := 5;<br /> cnt := 0;<br /> else<br /> cnt := cnt+1;<br /> end if;<br /> when 5 =><br /> data <="00000000";<br /> if cnt=5 then<br /> count := 6;<br /> cnt := 0;<br /> freq_ud <= '0';<br /> else<br /> cnt := cnt+1;<br /> freq_ud <= '1';<br /> end if;<br /> when 6 =><br /> dds_reset <= '1';<br /> if cnt=5 then<br /> count := 0;<br /> cnt := 0;<br /> else<br /> cnt := cnt+1;<br /> end if;<br /> when others =><br /> count :=0;<br /> end case;<br /> end if;<br /> end process;<br />end behavior;<br /> |
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